Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-12-19
2002-09-17
Elms, Richard (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S382000
Reexamination Certificate
active
06452227
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device having its bit line composed of a buried diffused impurity layer and a manufacturing method thereof, particularly to a silicidized semiconductor memory of mixed package type comprising a peripheral circuit area and a logic circuit area of a memory cell area.
2. Description of the Related Art
Non-volatile semiconductor memories designed for maintaining their stored information even when disconnected from their power sources, include EPROM, flash EPROM and the like, while logic semiconductor devices include MPU, MCU and the like, and it has been customary to manufacture them separately.
Concerning the non-volatile memory, the research and development of silicidized structures for further fining and further speeding of operation is in progress rapidly. On the other hand, from the similar reason, the transistors for logic circuit have also become to adopt the silicidized structure for the source/drain or the silicidized structure for the source/drain and the gate electrode (salicide structure).
Recently, the research and development of the mixed package semiconductor, characterized by having the non-volatile memory and the logic semiconductor device on a common substrate, is in progress rapidly. In consequence, it has become necessary even for the conventional mixed package semiconductor system to be silicidized.
The non-volatile memory, capable of making electrical writing and erasing, comprises a memory cell array area, a peripheral circuit area and a connection area and is formed on a substrate for semiconductor; however, the mixed package type semiconductor system further comprises a logic area including an SRAM or the like in addition to the above-mentioned components.
Concerning the memory cell array of the non-volatile memory, it has become necessary to reduce the number of steps of the manufacturing process thereof, and, as a suitable means for satisfying such a requirement, the buried bit line structure characterized by forming the diffused impurity layer on the surface of the substrate has been proposed.
Here, an example of conventional non-volatile memory, in which the memory cell array area has a buried bit line structure.
FIG. 1
is a schematic sectional view showing a memory cell of the memory cell array area and the selection transistor of the peripheral circuit area constituting the non-volatile memory having the buried bit-line structure.
The memory cell and the selection transistor are separated by a field oxidation film
108
; in the memory cell, as shown in
FIG. 2
for example, a first oxide film
120
, a charge storage silicon nitride film
121
, a second oxide film
122
and a word line (WL)
102
are accumulated sequentially on a semiconductor substrate
101
to form a gate electrode structure; in the selection transistor, a gate insulating film
111
and a gate electrode
112
are sequentially accumulated on the semiconductor substrate
101
to form a gate electrode structure.
In the memory cell, a bit line (BL)
103
is formed by ion implantation of impurities on a silicon substrate
101
; an insulation layer
104
is formed on the bit line
103
by means of thermal oxidation; the bit line
103
and a word line
102
are separated by the insulation layer
104
; the bit line
103
and source/drain
113
of the selection transistor
103
are connected to each other by a metal wiring
107
through a contact hole
105
opening on the surface of the bit line
103
and a contact hole
106
opening on the surface of the source/drain
113
, which are provided passing through the insulation layer
104
respectively.
Next, in the case of a non-volatile memory having a floating gate and a control gate disclosed in Japanese Patent Application Laid-Open No. 10-98170, the peripheral circuit and the bit line are connected by providing an impurity area.
In the case of the above-mentioned conventional non-volatile memory, if the memory cell array area is silicidized, this will cause a short circuit of the adjacent bit line
103
because of the presence of the silicide, and so only the peripheral circuit area, not including the bit line
103
, is silicidized. Therefore, in this case, only the memory cell array area is masked, but this process gives rise to a problem such as the complication of the manufacturing process.
Further, in the above case, in forming the metal wiring
107
, in the contact hole
105
of the memory cell, the surface of the unsilicidized bit line
103
is exposed, while in the contact hole
106
, the surface of the silicidized source/drain
113
is exposed. Thus, when forming the metal wiring
107
, one of the contact holes has its silicidized surface exposed while the other contact hole has its silicon substrate exposed. Therefore, one contact hole having the silicide exposed and the other contact hole having the substrate exposed exist concurrently, and so the before-burying treatment of the contact hole
106
on the silicidized side causes not only the damage to the exposed portion of the contact hole
105
on non-silicidized side but also the resultant poor contact and insufficient resistance.
SUMMARY OF THE INVENTION
An object of the present invention, made in consideration of the aforesaid problem of the related art, is not only to enable silicide in a buried bit line structure only for the peripheral circuit area (and logic circuit area) to be formed with ease and with reduced number of steps but also to resolve the problem resulting from the positional difference in the exposed portion of the opening between the two contact holes by connecting the memory cell array area and the peripheral circuit area (and the logic circuit area) with the second diffused impurity layer. Further, since the overlapped portion of the first diffused impurity layer and the second diffused impurity layer produces a high resistance, the silicide is formed to suppress the rise of the resistance. Such a high resistance results from that ions injected for forming the second diffused impurity layer will not sufficiently reach the end of the first diffused impurity layer because of the presence of the insulation layer formed on the top of the first diffused impurity layer, causing the formation of a narrow overlapped portion and resultant high resistance.
As mentioned above, an object of the present invention is to provide a highly reliable semiconductor memory and a manufacturing method thereof, which are designed for solving various problems resulting from the buried-bit-line structure and realizing a lower resistance, a higher fineness and operation at a higher speed.
The present inventor has arrived at the embodiments of the present invention given below by deliberately analyzing the present invention.
The present invention relates to a semiconductor memory device and a manufacturing method thereof, the semiconductor memory device having a so-called buried-bit-line structure, wherein the word line and the bit line intersect through the insulation layer to form the memory cell array area and the peripheral circuit area (a logical circuit area comprising a necessary transistor may be included additionally), and the first diffused impurity layer formed under the insulation layer.
The semiconductor memory according to the present invention is characterized in that a second diffused impurity layer is formed partially overlapping with one end of the first diffused impurity layer and that a silicide is formed on the surface of a third diffused impurity layer forming the surface layer of the second diffused impurity layer, including the overlapped portion, and the source/drain of the selection transistor.
In this case, a part of the second diffused impurity layer may be formed either commonly with or independently of one of the third diffused impurity layers, which constitute the source/drain.
For the memory cell and the selection transistor, the second diffused impurity layer and the third diffused impurity layer are connected by wiring through the silicide.
Hashimoto Hiroshi
Takahashi Koji
Armstrong Westerman & Hattori, LLP
Elms Richard
Fujitsu Limited
Smith Bradley
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