Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-10-02
2002-07-30
Elms, Richard (Department: 2824)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S534000, C438S255000, C438S398000, C438S964000
Reexamination Certificate
active
06426527
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory and a method for fabricating the same, and more specifically to a structure of a semiconductor memory of a one-transistor memory cell type having a stacked capacitor.
Recently, in a semiconductor memory such as DRAM (dynamic random access memory), a demand for reducing a required memory cell area is becoming strong in order to elevate the integration density.
One means for meeting with this demand is to provide each memory cell with a capacitor having a large capacitance per an occupying area. For this purpose, it was provided to form one of an upper electrode and a lower electrode of each capacitor, for example, the lower electrode of each capacitor, in the form of a cylinder, thereby increase the capacitance of the capacitance. Furthermore, it was proposed to form a number of hemi-spherical silicon grains (hemi-spherical grain silicon (HSG-Si)) on a surface of the cylindrical electrode to increase a surface area of the electrode, thereby to further increase the capacitance of the capacitance.
Here, a prior art structure of the semiconductor memory having the hemi-spherical grain silicon structure will be explained with reference to
FIG. 7
, which is a diagrammatic sectional view of the prior art semiconductor memory having the hemi-spherical grain silicon structure.
As shown in
FIG. 7
, the prior art semiconductor memory includes a P-type silicon substrate
3
and a gate oxide film (not shown), a gate electrode
22
and an N-type diffused layer
4
formed at a principal surface of the silicon substrate
3
. An interlayer insulating film
24
is formed to cover the silicon substrate
3
and the gate electrode
22
, and a silicon oxide film
12
is formed thereon.
The prior art semiconductor memory includes a through hole penetrating through the interlayer insulating film
24
and the silicon oxide film
12
to reach the N-type diffused layer
4
, and a phosphorus-doped polysilicon film is deposited by a CVD (chemical vapor deposition) process to fill the through hole, thereby to form a capacitor contact plug
21
.
On an upper end surface of the capacitor contact plug
21
, a lower electrode
31
in the form of an open-top, closed-bottom cylinder and formed of a doped polysilicon, is formed to have a predetermined thickness, and hemi-spherical silicon grains (HSG-Si)
31
A are formed on an inner surface of the cylindrical lower electrode
31
.
Between each two adjacent cylindrical lower electrode
31
formed in the semiconductor memory, a partition
11
is formed of an oxide film. For example, the partition
11
is formed of a stacked layer of a silicon oxide film
23
, a BPSG (borophosphosilicate glass) film
13
and an NSG (non-doped silicate glass) film
14
.
Now, a method for forming the HSG-Si polysilicon capacitor electrode will be explained also with reference to FIG.
7
.
As shown in
FIG. 7
, first, a silicon oxide film (field oxide)
3
A is formed on a principal surface of the P-type silicon substrate
3
by means of a LOCOS (local oxidation of silicon) process, and a gate oxide film (not shown) is formed on a device formation region confined by the silicon oxide film
3
A. Succeedingly, a gate electrode, a source region and a drain region are formed at the principal surface of the silicon substrate
3
. The interlayer insulating film
24
formed of the BPSG film and the silicon oxide film
12
are deposited on the whole surface of the substrate.
Thereafter, a through hole is formed to penetrate through the silicon oxide film
12
and the interlayer insulating film
24
to reach the N-type diffused layer
4
, and a phosphorus-doped polysilicon film is deposited to fill the through hole, thereby to form a capacitor contact plug
21
in contact with the N-type diffused layer
4
. Then, a silicon oxide film
23
, an insulating film
13
formed of a BPSG film and a silicon oxide film
14
formed of an NSG film are formed on the whole surface of the substrate in the named order. Succeedingly, a patterned resist is formed on the whole surface of the substrate by a photolithography, and the stacked insulating layer formed of the silicon oxide film
14
, the insulating film
13
and the silicon oxide film
23
, is etched to form a hole for formation of the lower electrode.
A doped polysilicon film is deposited on the whole exposed surface of the hole formed in the stacked insulating layer, to form the cylindrical lower electrode
31
.
Thereafter, hemi-spherical silicon grains (HSG-Si)
31
A are formed and grown on an inner surface of the cylindrical lower electrode
31
by the CVD process.
Here, in order to prevent a short-circuiting between adjacent lower electrodes
31
, the hemi-spherical silicon grains (HSG-Si)
31
A formed on the upper portion of the lower electrode
31
are removed. For this purpose, specifically, an acid washing and an etching are carried out for the hemi-spherical silicon grains (HSG-Si)
31
A and the NSG film
14
forming an upper portion of the partition
11
. The degree of the acid washing carried out at this time is controlled to the effect that the NSG film
14
is slightly projected, and the etching is an overetching
On the lower electrode
31
formed as mentioned above, a dielectric film formed of an insulating film and an upper electrode (both not shown) are formed in the named order. Thus, the semiconductor memory is fabricated.
However, the following problems were encountered in the prior art semiconductor memory having the hemi-spherical grain silicon structure:
First, the hemi-spherical silicon grains (HSG-Si)
31
A are flaked off from the surface of the lower electrode in the acid washing carried out later, and the flaked-off hemi-spherical silicon grains nidate on an upper portion of the partition, with the result that a short-circuiting occurs between adjacent lower electrodes, namely, between adjacent memory cells.
If this short-circuiting occurs, the semiconductor memory so configured to store one bit of information per one memory cell, becomes defective. If the lower electrodes of the memory cells of two bits are short-circuited, unless the same data is stored in the memory cells of two bits, an electric charge store in one memory cell flows to the other memory cell, with the result that a potential of the one memory cell drops, and therefore, a reading error occurs at the time of a data reading.
Secondly, in the prior art, the doped polysilicon was etched back by an overetching in order to prevent the short-circuiting between adjacent memory cells. As a result, the hemi-spherical silicon grains (HSG-Si)
31
A are flaked off from an inner surface of the cylindrical lower electrode, so that there are produced a large number of semiconductor memories that do not have a desired memory cell capacitance as a product. Namely, a yield of production drops.
BRIEF SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a semiconductor memory and a method for fabricating the same, which have overcome the above mentioned problems of the prior art.
Another object of the present invention is to provide a semiconductor memory and a method for fabricating the same, capable of preventing a short-circuiting between the adjacent cylindrical lower electrodes. without reducing the capacitance of the memory cell.
The above and other objects of the present invention are achieved in accordance with the present invention by a semiconductor memory having a number of stacked capacitor memory cells each having a cylindrical lower electrode which is in the form of a cylinder having an open top and a closed bottom and which is formed of a doped polysilicon having a predetermined thickness, the cylindrical lower electrode having a hemi-spherical grain silicon formed on an inner surface of the cylindrical lower electrodes, wherein an upper end of a partition, which is formed of an insulating material between adjacent cylindrical lower electrodes, has a shape preventing a nidation of a silicon grain of the hemi-spherical grain silicon.
With the a
Elms Richard
Foley & Lardner
NEC Corporation
Wilson Christian D.
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