Exception reporting architecture for SIMD-FP instructions

Details Exception reporting architecture for SIMD-FP instructions Exception reporting architecture for SIMD-FP instructions

1998-10-12

2002-04-23

Eng, David Y. (Department: 2155)

Electrical computers and digital processing systems: processing

Processing control

Branching

C712S205000

Reexamination Certificate

active

06378067

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to computer systems. In particular, the invention describes an improved method for handling exceptions generated in a processing system.
2. Background Information
The increased use of graphics and sound in computer applications has resulted in a substantial increase in the amount of data that modem computer systems, particularly multi-media personal computers handle. Many of these computer systems have implemented a single instruction, multiple data (SIMD) architecture to improve the efficiency of multi-media applications, as well as other applications with similar characteristics. SIMD architectures enable one instruction to operate on several operands simultaneously, rather than on a single operand. In particular, SIMD architectures take advantage of packing many data elements or segments within one register or memory location. With parallel hardware execution, multiple operations can be performed on separate data elements with one instruction, resulting in a significant performance improvement.
In many graphics applications, specifically three-dimensional (“3D”) graphics applications, there are manipulations of scenes that have objects such as triangles and polygons which are rotated, scaled, etc. The range of numbers in, for example, a 32-bit register is from zero to (2
32
−1). However, in many instances, the values of the objects may need to be represented by a floating point number because a bigger number range is required or the number is not a whole number (e.g., due to the introduction of angles). Therefore, these values must be converted to floating point numbers and moved to the floating point registers.
Computations in floating point (FP), unlike computations in integers can result in exceptions. Such exceptions are defined by the American National Standards Institute (ANSI) and Institute of Electrical and Electronic-Engineers (IEEE) in ANSI/IEEE standard No. 754-1985 approved July of 1985, hereinafter IEEE standard. Each element of an operand processed may produce one or more exceptions. Because SIMD processes multiple data elements of an operand, the processing of floating point data using a circuit based on SIMD architecture may result in multiple interrupts or “exceptions” issued by the processor. Exceptions are interrupts that originate in the processor itself. The cause of an exception is generally an internal processor error caused by software that can no longer be handled by the processor alone.
Exceptions include fault exceptions and trap exceptions. Fault exceptions, or “faults,” are exceptions which are issued prior to completing an instruction. Thus, a fault exception prevents a result from being computed for an operation or instruction. In some instances, faults can be detected prior to the starting of the computation. Traps exceptions, or “traps,” are issued after completion of an instruction. Traps indicate that an instruction has been executed but that the program should be interrupted to check or correct certain parameters, including possibly the result produced by execution of the instruction.
When a single instruction operates on several data elements simultaneously, several exceptions may be simultaneously produced. Current computer designs do not efficiently handle the multiple exceptions that are produced. Such systems typically (1) slow the system down to handle the exceptions, and/or (2) do not meet Institute of Electrical and Electronic Engineers (IEEE) floating-point standards, specifically IEEE standard No. 754-1985 approved in 1985, for exception reporting.
Thus, an improved method and apparatus for handling multiple exceptions generated during an SIMD operation is needed.
SUMMARY OF THE INVENTION
A method of handling operations on at least one operand having a first data element and a second data element is described. An operation is performed on the first data element and the occurrence of a first exception detected. The operation is also performed on the second data element and the occurrence of a second exception is detected. The occurrence of the first exception and the second exception are communicated to the exception handler prior to the processing of either the first or the second exception.


REFERENCES:
patent: 6038652 (2000-03-01), Phillips et al.
patent: 6058469 (2000-05-01), Baxter

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