Method for forming polycide gate electrode of metal oxide...

Details Method for forming polycide gate electrode of metal oxide... Method for forming polycide gate electrode of metal oxide...

1999-06-29

2002-05-14

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S653000, C438S664000, C438S302000, C438S520000, C438S926000, C438S280000

Reexamination Certificate

active

06387788

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor and, more particularly, to a method for fabricating a metal oxide semiconductor field effect transistor (MOSFET) having a polycide gate electrode.
DESCRIPTION OF THE PRIOR ART
In the prior art, a polycide, which is stacked with a polysilicon or a tungsten-silicide/polysilicon, has been used as a gate electrode of metal oxide semiconductor field effect transistor (MOSFET). However, as the density of semiconductor devices increases, a line width of gate electrode becomes narrower. So conventional electrode materials may not satisfy low resistance required in high-integrated devices. Accordingly, silicide-type materials such as TiSi
2
, CoSi
2
, VSi
2
, ZrSi
2
, NbSi
2
, MoSi
2
and HfSi
2
have been developed as a substitution for single polysilicon materials. As of now, titanium silicide (TiSi
2
) relatively well satisfies requirements for the gate electrode such as a low resistivity, a high melting point, an easiness of forming a thin layer and a line pattern, a thermal stability and so on. So, the titanium silicide (TiSi
2
) is considered to be remarkable.
FIGS. 1A
to
1
F are cross-sectional views illustrating a conventional MOSFET to which a titanium silicide is applied.
First, a gate oxide layer
2
is grown on a substrate
1
and a polysilicon layer
3
having a low resistivity is deposited on the gate oxide layer
2
by using the LPCVD (low-pressure chemical vapor deposition) method, and then a titanium layer
4
is deposited on the polysilicon layer
3
, as shown in FIG.
1
A.
Next, by performing a RTP (rapid thermal process) for a few seconds, in a nitrogen atmosphere and at a specific temperature, a titanium silicide layer
5
having a low resistivity is formed by a reaction between the titanium layer
4
and the polysilicon layer
3
, as shown in FIG.
1
B.
A mask oxide layer
6
is deposited on the titanium silicide layer
5
, so that the titanium silicide layer
5
may be protected when sidewall spacers are formed by a following dry-etching process, as shown in FIG.
1
C.
Subsequently, a gate electrode is patterned by applying mask and etching processes to the mask oxide layer
6
, the titanium silicide layer
5
, the polysilicon layer
3
and the gate oxide layer
2
, as shown in FIG.
1
D.
A screen oxide layer
7
is grown on the exposed substrate
1
by a thermal process, so that it may protect a damage to the substrate
1
when a source/drain region is formed by ion implantation, as shown in FIG.
1
E.
Finally, the lightly doped source/drain region
8
is formed by a low-density ion implantation, as shown in FIG.
1
F. Next, after forming sidewall spacers on the sidewall of gate, a heavily doped drain/source region is formed by a high-density ion implantation after the formation of a LDD (lightly doped drain) structure.
FIGS. 2A
to
2
C are cross-sectional views showing problems caused by the prior art. Referring to
FIG. 2A
, a titanium nitride layer
9
, which is undesirable, is formed between the titanium silicide layer
5
and the mask oxide layer
6
. The reason for the formation of the titanium nitride layer
9
is that the RTP (rapid thermal process) shown in
FIG. 1B
is performed in a nitrogen atmosphere. That is, the titanium nitride layer
9
is easily formed since titanium easily reacts with nitrogen.
FIG. 2B
shows another problem caused by the formation of the titanium nitride layer
9
shown in FIG.
2
A. That is, when the screen oxide layer
7
is grown, the sidewalls of the gate electrode structure, which include a polysilicon/titanium-silicide, as well as the substrate
1
are simultaneously oxidized, thereby forming an abnormal oxide layer. At this time, since the titanium nitride layer
9
is very easily oxidized, a thick oxide layer
10
, which is abnormally grown, is formed on the side of the titanium nitride layer
9
. In particular, the LDD (lightly doped drain) region may have an abnormal ion-implantation profile since the thick oxide layer
10
acts as a barrier in performing the ion implantation, as shown in FIG.
2
C.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method for fabricating an improved gate electrode of a MOSFET device.
In accordance with an aspect of the present invention, there is provided a method for fabricating a MOSFET device having a polycide gate to which a titanium silicide is applied, comprising the steps of sequentially forming a polysilicon layer on a gate insulating layer and a titanium layer in this order, forming a capping layer on the titanium layer and forming a titanium silicide layer by performing a rapid thermal process in nitrogen environment


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