Method and apparatus in a data processing system for using chip

Details Method and apparatus in a data processing system for using chip Method and apparatus in a data processing system for using chip

1996-02-28

1998-09-01

Gossage, Glenn

Electrical computers and digital processing systems: memory

Addressing combined with specific memory configuration or...

711147, 711170, 711209, 36523006, 326105, G06F 1200, G11C 11407, G11C 11413, H03K 190175

Patent

active

058025413

ABSTRACT:
A data processing system (10) including a chip select circuit (40) which allows flexible attribute protection, and a method for providing a plurality of chip select signals in the data processing system are disclosed. Each of two or more decoders (42, 48) determines whether a bus cycle address is within a programmable region and matches one or more programmable attributes, and if so activates a corresponding match signal. A logical operation circuit (60) then selectively causes a chip select signal (72) to be activated in response to a logical operation performed on the match signals. In one embodiment, the logical operation circuit (60) may cause the chip select signal (72) to be activated if either of two match signals (47, 53) is activated, allowing for example the same region of memory to be accessed from two address spaces using the same chip select signal (72).

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