Semiconductor device

Details Semiconductor device Semiconductor device

2001-02-27

2002-09-17

Ho, Hoai (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S378000, C257S379000, C257S368000

Reexamination Certificate

active

06452272

ABSTRACT:

The invention relates to a semiconductor device comprising a body of insulating material, which body of insulating material has a surface to which a semiconductor element and an interconnect structure are fastened, which interconnect structure is disposed between the semiconductor element and the body of insulating material and has a superficial patterned metal layer facing the body of insulating material, which superficial patterned metal layer comprises conductor tracks.
Such a semiconductor device is particularly suited for processing signals of very high frequencies. The semiconductor element may be a single diode or a single transistor, but it may alternatively be an integrated circuit comprising a large number of transistors. The interconnect structure may serve for the electrical connection of the semiconductor element to other semiconductor elements and may be provided with contact portions (bonding pads) to enable electrical contact of the semiconductor device to the external world, but may also comprise passive elements such as inductors, capacitors and resistors.
In practice, the semiconductor device can be mounted on a customary printed circuit board (PCB) or accommodated in a customary envelope. The mounting surface of the printed circuit board as well as the inside of the envelope are provided with an interconnect structure comprising conductor tracks for electrically contacting the semiconductor device. The body of insulating material is hence sandwiched between the interconnect structure of the semiconductor device and the interconnect structure present on the printed circuit board or inside the envelope, so that parasitic capacitances between these interconnect structures are small. As a result, parasitic currents flowing during the processing of high-frequency signals are small. By virtue thereof, the power consumption of the semiconductor device is small, which is particularly advantageous for application in mobile telephony, where signals with a frequency in the order of 1 GHz must be processed and the power must be supplied by batteries. The power consumption of a semiconductor device mentioned above may be a factor of 20 smaller than that of a customary semiconductor device, which is formed on an ordinary, relatively thick body of semiconductor material.
A semiconductor device of the kind mentioned in the opening paragraph is known from U.S. Pat. No. 5,646,432, in which the interconnect structure of the semiconductor device is covered by an insulating layer of silicon oxide or silicon nitride in a thickness of preferably 2 &mgr;m, and a planarizing layer of preferably less than 2 &mgr;m is provided between this insulating layer and a layer of an adhesive having a thickness in the range between 10 and 20 &mgr;m.
Although parasitic capacitances between the interconnect structure of the semiconductor device and the interconnect structure present on a printed circuit board or inside an envelope are already small, it is desirable to minimize them as far as possible in connection with the power consumption of the semiconductor device. If, for example, a body of glass having a dielectric constant ∈
r
of approximately 6.5 and a thickness of 400 &mgr;m is used as the body of insulating material, then the parasitic capacitance between a 1 &mgr;m wide conductor track of the interconnect structure of the semiconductor device and the interconnect structure present on the printed circuit board or inside the envelope amounts to approximately 26.10
−18
F per &mgr;m of length of the conductor track. The use of a thicker body of glass is impractical, as a doubling in thickness to 800 &mgr;m only results in a reduction of the parasitic capacitance by approximately 10%. Moreover, a body of insulating material with a thickness of 800 &mgr;m results in a semiconductor device with an impractical thickness, as no use can be made of equipment which is customarily employed for enveloping semiconductor devices provided on conventional semiconductor wafers. In addition, the parasitic capacitance can be reduced by employing a body with a dielectric constant ∈
r
which is lower than that of glass. However, this is not always a practical solution, as a body of such a material, for example quartz, is in general more expensive.
It is an object of the invention to further reduce the power consumption of a semiconductor device of the kind mentioned in the opening paragraph without the necessity of employing a body of insulating material of impractical thickness or a body of an impractical material.
According to the invention, this object is achieved in that an insulating layer having a dielectric constant ∈
r
below 3 is disposed between the superficial patterned metal layer of the interconnect structure and the body of insulating material, and an insulating barrier layer is disposed between the semiconductor element and the insulating layer having a dielectric constant ∈
r
below 3, so as to counteract that contaminants from the insulating layer having a dielectric constant ∈
r
below 3 cannot reach the semiconductor element.
The invention is based inter alia on the insight, that the size of the parasitic capacitances is predominantly determined by the dielectric constant ∈
r
of the dielectric which is closest to the conductor tracks of the interconnect structure of the semiconductor device, and that the use of a relatively thin layer of a material having a relatively low dielectric constant ∈
r
between the interconnect structure of the semiconductor device and the body of insulating material already results in a relatively large reduction of the parasitic capacitances. By using an insulating layer having a dielectric constant ∈
r
of about 2.5 and a thickness of approximately 25 &mgr;m, the parasitic capacitance, as in the above-mentioned example, between a 1 &mgr;m wide conductor track of the interconnect structure of the semiconductor device and the interconnect structure present on the printed circuit board or inside the envelope is reduced by 40% when use is made of a 400 &mgr;m thick body of glass with a dielectric constant ∈
r
of 6.5. The power consumption of the semiconductor device is reduced by practically the same percentage. Such a low dielectric-constant layer often comprises organic material, which organic material generally represents a source of contaminants such as alkali ions. These contaminants may reach the semiconductor element and adversely influence the performance of the semiconductor element. Hence, in order to counteract a reduction in the stability of the semiconductor element owing to the presence of the insulating layer having a dielectric constant ∈
r
below 3, an insulating barrier layer is disposed between the semiconductor element and the insulating layer having a dielectric constant ∈
r
below 3.
Although the insulating barrier layer may be disposed between the insulating layer having a dielectric constant ∈
r
below 3 and the superficial patterned metal layer of the interconnect structure, it is advantageously disposed between the superficial patterned metal layer and the semiconductor element. In this way, one layer is saved during the manufacture of the semiconductor device.
It is advantageous that the insulating barrier layer is a plasma-deposited layer. It is evident to a person skilled in the art that, although other deposition techniques such as, for example, sputter deposition may give satisfactory results, plasma-assisted deposition techniques such as plasma-enhanced chemical vapor deposition (PECVD) and electron cyclotron resonance (ECR) plasma chemical vapor deposition (CVD) are pre-eminently suited for the deposition of the insulating barrier layer. Plasma-assisted deposition techniques enable the provision of layers at very low temperatures, that is to say at temperatures between about 100° C. and 400° C. in the case of PECVD and at temperatures between room temperature and about 150° C. in the case of ECR plasma CVD, by reacting the gases in a glow discharge, which suppl

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