Memory controller with timing constraint tracking and...

Details Memory controller with timing constraint tracking and... Memory controller with timing constraint tracking and...

1999-07-02

2002-09-17

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S163000, C711S168000, C712S029000

Reexamination Certificate

active

06453401

ABSTRACT:

BRIEF DESCRIPTION OF THE INVENTION
The present invention relates generally to devices that control memory operations in memories of digital systems. In particular, it pertains to a memory controller that has a timing constraint checking unit to check timing constraints imposed on commands to access a memory.
BACKGROUND OF THE INVENTION
Commands (a.k.a. requests) to access a DRAM (dynamic random access memory), such as precharge, activate and column access commands, require a certain amount of time to complete. This means that a command to access the DRAM should be issued only when the DRAM is known to be in a state that is suitable for this access and all previous commands that have a bearing on this command have been completed. These two restrictions result in what are known as timing constraints.
A DRAM memory subsystem may include multiple devices and each device will typically include multiple banks of memory cells. When a command to access a bank of a device is issued, timing constraints are imposed on subsequent commands to access the same bank or a different bank of the device. Before a subsequent command can be issued, the timing constraints that are imposed on it by previous commands must all be satisfied. The number and duration of the timing constraints that can be imposed on a command depends on the type of command, the bank or device being accessed, process parameter values, and the DRAM technology.
Table 1 and
FIG. 1
disclose and illustrate the types of timing constraints that are imposed on commands for accessing a DRAM. Trcd, Tss, and Trasmin constraints are all imposed when an activate command for a row of a bank of a device is issued. The Tss constraint is imposed on an activate command for a different row of the same bank or a row of a different bank of the device. The Trcd constraint is imposed on a subsequent column command for any column of the same bank. The Trasmin constraint is imposed on a subsequent precharge command for the same bank. Thus, the Tss constraint is imposed at the device level while the Trcd and Trasmin constraints are imposed at the bank level. When a column operation for a column of a bank of a device is issued, a Tcps constraint is imposed on a subsequent precharge command for the same bank. The Tcps constraint is therefore imposed at the bank level. Finally, Trp and Tpp constraints are imposed when a precharge command for a bank of a device is issued. The Trp constraint is imposed at the bank level on an activate command for a row of the same bank. The Tpp constraint is imposed at the device level on a precharge command for the same bank or a different bank of the same device.
TABLE 1
Maximum
Constraint
Constraint
Type
Time
Description
Trcd
30 ns
Minimum time imposed between an activate
command for any row of a bank of a device and a
column command for a column of the same bank.
Trasmin
60 ns
Minimum time imposed between an activate
command for a row of a bank of a device and a
precharge command for the same bank.
Tss
20 ns
Minimum time imposed between an activate
command for a row of a bank of a device and an
activate command for a different row of the
same bank or a row of a different bank of the
same device.
Tpp
20 ns
Minimum time imposed between a precharge
command for a bank of a device and a
precharge command for the same or different
bank of the same device.
Trp
20 ns
Minimum time imposed between a precharge
command for a bank of a device and an
activate command for a row of the same bank.
Tcps
20 ns
Minimum time imposed between a column
command for a column of a bank of the
device and a precharge command for the
same bank.
In the design of a typical DRAM controller, performance is often traded for design simplicity. For example, all commands to access a DRAM may be separated by the largest constraint time of the timing constraints. Since the Trasmin constraint in Table 1 has the largest constraint time, the controller may be hard wired so that all commands are separated by the Trasmin constraint time. This obviously reduces the complexity of the controller. But, the controller's performance is reduced since commands that can be issued earlier are delayed.
In view of the foregoing, it would be highly desirable to provide a DRAM controller that is capable of simultaneously tracking and checking each and every timing constraint applicable to a set of DRAMs. Ideally, the controller would have a simple design and provide high performance and flexibility in controlling access to various DRAMs with the same type of timing constraints but different constraint times.
SUMMARY OF THE INVENTION
A memory controller includes a constraint tracking and checking unit. Timing constraints are imposed by respective issued commands to access a memory. These commands are issued by a command issue unit in the controller.
The constraint tracking and checking unit has a constraint tracking subunit that includes multiple tracking circuits and an allocation circuit. The allocation circuit is configured to allocate a selected tracking circuit from among the multiple tracking circuits each time that a specific command is issued. The selected tracking circuit is configured to track the timing constraint imposed by the specific command.
The constraint checking subunit is configured to check if the tracked timing constraint is pending against issuance of a generated command to access the memory. This command is generated by a command generation unit in the controller.
The constraint checking subunit may have multiple checking circuits, with each checking circuit corresponding to one of the tracking circuits. The checking circuit that corresponds to the allocated tracking circuit is configured to check if the tracked timing constraint is pending against issuance of the generated command.
The allocated tracking circuit may be configured to count time to a predefined constraint time for the specific timing constraint type and generate a timeout signal (also called a timing constraint status signal or a timeout status signal) indicating whether the tracked timing constraint has expired. The allocated tracking circuit may also be configured to store an address contained in the issued command that identifies a part of the memory to which the tracked timing constraint applies.
The checking circuit corresponding to the allocated tracking circuit is therefore configured to check if the timing constraint is pending against issuance of the generated command in the following manner. First, it compares an address contained in the generated command and the address stored by the address register of the selected tracking circuit. Second, if there is a match, it determines from the timeout signal of the timer of the selected tracking circuit whether the timing constraint has expired. The checking circuit generates a constraint pending signal (also called a blocking signal) when a constraint is pending against the generated command.
Each of the tracking circuits may include a timer and an address register. The timer of the allocated tracking circuit is configured to count time to the predefined constraint time and generate the timeout signal. The address register of the allocated tracking circuit is configured to store the address contained in the issued command.
The constraint tracking and checking unit may further include a programmable register that is programmed to store a parameter value representing the predefined constraint time. The timer of the allocated tracking circuit is further configured to load the parameter value when the allocated tracking circuit is allocated. It then counts time to the predefined constraint time by counting up to or down from the parameter value.
The allocation circuit may be further configured to identify allocatable tracking circuits of the multiple tracking circuits in response to the parameter value. The number of allocatable tracking circuits will be sufficient to ensure that at least one of the allocatable tracking circuits will always be available for allocation each time that one of the issued commands is issued. The alloc

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