Memory-cell array and a method for repairing the same

Details Memory-cell array and a method for repairing the same Memory-cell array and a method for repairing the same

1997-04-08

1998-07-28

Zarabian, A.

Static information storage and retrieval

Read/write circuit

Bad bit

365149, 365226, G11C 140

Patent

active

057870446

ABSTRACT:
An array of memory cells are arranged in rows and columns. The array includes a plurality of cell plates that are each coupled to at least one of the memory cells. A generator produces a bias voltage. A plurality of isolation circuits are each coupled between the generator and one or more of the cell plates. Each isolation circuit provides the bias voltage to the cell plate or plates to which the isolation circuit is coupled. The cell plates may be coupled to memory cells from a plurality of the columns. Additionally, each of the isolation circuits may selectively provide, in response to a control signal, the bias voltage to the cell plate or plates to which the isolation circuit is coupled.

REFERENCES:
patent: 5079743 (1992-01-01), Suwa
patent: 5079746 (1992-01-01), Sato
patent: 5235550 (1993-08-01), Zagar
patent: 5301143 (1994-04-01), Ohri et al.
patent: 5373463 (1994-12-01), Jones
patent: 5450360 (1995-09-01), Sato
patent: 5469391 (1995-11-01), Haraguchi

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