Semiconductor memory device performing redundancy repair...

Details Semiconductor memory device performing redundancy repair... Semiconductor memory device performing redundancy repair...

2001-07-18

2002-05-14

Mai, Son (Department: 2818)

Static information storage and retrieval

Read/write circuit

Testing

C365S200000

Reexamination Certificate

active

06388929

ABSTRACT:

TITLE OF THE INVENTION
Semiconductor Memory Device Performing Redundancy Repair Based on Operation Test and Semiconductor Integrated Circuit Device Having the Same
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, more particularly, to a system LSI on which a memory is mounted. More specifically, the invention relates to the configuration of a memory core capable of executing redundancy repair on the basis of an operation test without using a fuse device.
2. Description of the Background Art
A system LSI such as a logic merged DRAM, in which a logic such as a processor or an ASIC (Application Specific Integrated Circuit) and a dynamic random access memory (DRAM) of a mass storage capacity are integrated on the same semiconductor chip (semiconductor substrate) has been developed. In such a system LSI, the logic and the memory such as a DRAM are connected to each other via a multi-bit internal data bus of 128 to 512 bits, thereby enabling data transfer speed higher than that of a general purpose DRAM by at least one or two orders of magnitude to be realized.
The DRAM and the logic are connected to each other via an interconnection. Since the interconnection is sufficiently shorter and has a small parasitic impedance than an on-board interconnection, a large reduction in charging/discharging currents in a data bus as well as high-speed signal transfer can be realized. As compared with a method of attaching a general purpose DRAM on the outside to the logic, the number of pin terminals on the outside of the logic is smaller.
For these reasons, the system LSI such as a logic merged DRAM largely contributes to higher performances of information devices for executing processes dealing with various data such as three-dimensional graphics process and image and audio process.
In such a system LSI, an increase in capacity and an increase in the number of kinds of memory cores to be mounted are conspicuous in the stream of forming a system on a chip. On a general memory, a redundancy circuit for replacement repairing a defective memory cell with a spare memory cell is mounted to assure a good yield as a design rule becomes finer in correspondence with larger capacity and higher packing density. Similarly, such a redundancy circuit has to be mounted on a memory core which is mounted on a system LSI.
In order to execute redundancy repair, it is necessary to conduct an operation test on a memory core as a target to be tested to thereby specify a defect address corresponding to a defective memory cell from the result of the operation test. Generally, the defect address is programmed in the memory core by blowing a fuse by using a laser trimming apparatus or the like. In normal operation, an input address is compared with a defective address. When they coincide with each other, by accessing a spare memory cell in place of a regular memory cell, the redundancy repair using a redundancy circuit is conducted.
When an operation test on a memory core mounted on a system LSI is carried out via a logic unit, it is feared that a test of an operation timing margin or the like on the memory cannot be accurately performed and that a sufficient test cannot be conducted since the number of test patterns generated by the logic is limited from the viewpoint of a program capacity. What is called a direct memory access test for directly testing a memory core such as a DRAM core from the outside of a system LSI via a dedicated tester such as a memory tester is therefore conducted.
FIG. 26
is a block diagram for explaining the direct memory access test using a test interface circuit.
Referring to
FIG. 26
, a DRAM core
500
as a target to be tested operates in response to a command control signal inCMD and an address signal inADD which are received from a selector
504
and an operation clock DCLK received from a gate
506
. The DRAM core
500
receives write data inDin and outputs read data inDout.
A test interface circuit TIC receives a test clock TST_CLK, a test command signal TST_CMD, a test address signal TST_ADD and test input data TST_Din from a memory tester as an external tester and outputs test output data TST_Dout to the memory tester.
In a manner similar to a general DRAM, each of the test input data TST_Din supplied to the test interface circuit TIC and the test output data TST_Dout outputted from the test interface circuit TIC is set to have a bit width of, for example, 8 bits. On the other hand, the bit width of the DRAM core
500
is as wide as, for example, 256 bits. The test interface circuit TIC expands the 8-bit test input data TST_Din to 256-bit write data TST_Din, selects data of 8 bits from the 256-bit test output data TST_Dout from the DRAM core and outputs the data as the test output data TST_Dout to the memory tester.
In normal operation, the gate
506
supplies a clock signal CLK which is sent from the logic unit as the operation clock DCLK to the DRAM core
500
. On the other hand, in a test mode, the gate
506
supplies the test clock TST_CLK which is received from the memory tester as the operation clock DCLK to the DRAM core
500
.
The test interface circuit TIC receives the test command signal TST_CMD and the test address signal TST_ADD from the memory tester at a timing synchronized with the test clock TST_CLK and outputs a test command signal TIC-CMD and a test address signal TIC-ADD. The group of signals generated by the test interface circuit TIC is supplied to the selector
504
. The selector
504
also receives a logic command, a logic address and a logic data input from the logic unit.
The selector
504
operates in response to a test mode entry signal TE. The test mode entry signal TE is activated in the test mode and is inactivated in normal operation. In normal operation, therefore, the selector
504
supplies the command signal and the address signal from the logic unit as signals inCMD and inADD to the DRAM core
500
. On the other hand, in the test mode, the selector
504
supplies the test command signal TIC-CMD and the test address signal TIC-ADD which are supplied from the test interface circuit TIC as the internal command signal inCMD and the address signal inADD to the DRAM core
500
.
By providing such a test interface circuit TIC, an external memory tester can directly access the DRAM core
500
. Consequently, the direct memory access test can be carried out. A necessary operation test on the DRAM core
500
can be therefore conducted by using a general SDRAM memory tester.
For a system LSI on which a plurality of memory cores are mounted, however, when the direct memory access test using the test interface circuit TIC as described above is adopted, the operation test for redundancy repair has to be sequentially executed on the plurality of memory cores. The number of operation tests for redundancy repair is therefore large. Since the test interface circuit has to be disposed in correspondence with each of the memory cores, it increases the chip size.
For avoiding such problems, a technique of providing a DRAM core with what is called a BIST (Built In Self Test) function so that the DRAM core itself conducts an operation test is known.
FIG. 27
is a schematic block diagram showing the configuration of a conventional DRAM core
510
having the BIST function.
Referring to
FIG. 27
, the DRAM core
510
comprises: a control circuit
20
which receives the command control signal CMD and the address signal ADD and controls the whole operations of the DRAM core
510
; a memory cell array
30
in which memory cells are arranged in a matrix; a decoding circuit
40
for selecting a memory cell according to the address signal; a data path band
50
for amplifying data read from the memory cell and writing write data to the memory cell array
30
; and an input/output buffer
60
for receiving/outputting input/output data between the DRAM core and the outside of the DRAM core.
The memory cell array
30
is divided into a plurality of memory mats MAO to MAn (n: natural number). Each memor

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