Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2001-05-29
2002-07-30
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S082000, C326S017000
Reexamination Certificate
active
06426653
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to output drivers generally and, more particularly, to an output driver using MOS technology that is configured to operate using either a 3 volt or 5 volt supply voltage.
BACKGROUND OF THE INVENTION
For integrated circuits operating at a relatively high supply voltage (e.g., a TTL voltage such as 5 volts), it is advantageous to have an NMOS output pullup driver. The NMOS output driver reduces system power by not pulling the output all the way up to the supply voltage. Integrated circuits operating with a relatively low supply voltage (e.g., 3 volts) typically use CMOS voltage levels and are therefore generally required to pull their outputs up to voltages near the supply. This is usually accomplished using a PMOS pullup transistor.
It is desirable to have a single part that can be programmed using fuses, or some other type of step late in the fabrication process, to configure the part to operate using either 5 volt or 3 volt supply voltages. One implementation may be realized by providing two independent pullup sections. The first pullup would be an NMOS pullup while the second pullup would be a PMOS pullup. The late configuration would configure the appropriate pullup for the desired voltage operation. However, this would require the output section to generally duplicate the pullups which would result in a larger chip.
Implementing a single pullup device for use with both 3 volt and 5 volt input supply voltages may reduce the overall die size. One alternative to such an implementation would be using an NMOS pullup with a boot strapped gate. Another implementation may be a PMOS pullup with an additional circuit to turn off the PMOS pullup after the output has been pulled up to the desired voltage. One way of implementing the PMOS pullup approach is to connect the pullup as a diode for 5V operation. However, the size of the PMOS pullup is generally (and usually undesirably) determined by the larger 5 volt part rater than the smaller 3 volt part.
SUMMARY OF THE INVENTION
The present invention concerns a circuit and method for providing a fast transitioning output buffer configured for low voltage operation (e.g., a 3 volt supply voltage) with the same output devices as for a high voltage operation (e.g., a 5 volt supply voltage). In one embodiment, the circuit lowers the gate voltage on a P-channel pullup while the output is being pulled up. In another embodiment, the circuit raises the gate voltage on an N-channel pulldown as the output is pulled down. As a result, MOS devices configured for low voltage operation (e.g., 3 volt) may be used as pullup and pulldown devices in a relatively high operating voltage environment (e.g., 5 volts) in the absence of devices configured to operate at the high voltage (e.g., having an increased size relative to a device configured for 3 volt operation).
The objects, features and advantages of the present invention include providing a 5V output driver that uses the same PMOS pullup and NMOS pulldown as a 3V output driver, does not require a larger PMOS device to support the 5 volt operation, provides a fast output transition and has a reduced final pullup voltage.
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Christopher P. Maiorana P.C.
Cypress Semiconductor Corp.
Tokar Michael
Tran Anh
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