Methods for manufacturing semiconductor devices

Details Methods for manufacturing semiconductor devices Methods for manufacturing semiconductor devices

1999-11-11

2002-07-09

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S197000, C438S595000

Reexamination Certificate

active

06417083

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor devices and methods for their manufacture, and more particularly, certain embodiments relate to etching of a conductive layer containing silicon.
BACKGROUND
In a method for manufacturing a semiconductor device, formation of a gate electrode, for example, is performed by etching a part of a conductive layer such as a polysilicon layer formed on a semiconductor substrate through a dielectric layer. The etching is performed by a photolithographic method by using a desired resist pattern for obtaining desired shapes and dimensions. Accordingly, to obtain a desired photo pattern is an important technology for formation of gate electrodes. However, with recent reduction in size of gate electrode structures, the following phenomenon occurs at steps of edges of an element isolation region when a resist is subjected to an exposure. Referring to
FIGS. 10 and 11
, the phenomena will be explained.
FIG. 10
is a cross-sectional view when a gate electrode is formed adjacent to an element isolation region of a semiconductor device. A first step
130
a
exists at an edge near a gate oxide film
124
of an element isolation region
112
formed on a silicon substrate
110
. When a polysilicon layer
126
is deposited on the element isolation region
112
and the gate oxide film
124
, a second step
130
b
is created on the polysilicon layer
126
located over the first step
130
a
. When the second step
130
b
exists, for example, the following problem occurs.
For etching a predetermined pattern in the polysilicon layer
126
, dry etching is performed by the use of a mask having a pattern generally formed by a resist. A patterning of the resist is performed by exposing and developing the resist. Accordingly, when a region indicated by the chained lines between A and B in a resist layer R
1
shown in
FIG. 10
is removed, only the resist layer region R
1
a
need be exposed in the case of using a positive resist. When the resist layer region R
1
a
indicated by the chained lines between A and B is exposed, exposure light penetrates through the resist layer region R
1
a
and is reflected at an interface between the resist layer R
1
and the polysilicon layer
126
. Therefore, reflected light at a horizontal portion of a surface of the polysilicon layer
126
, such as a first exposure light
140
a
, advances in a direction opposite to that of the incident light. While reflected light at the second step
130
b
, such as a second exposure light
140
b
, advances in various directions corresponding to tilting angles of the second step
130
b
, the incident light penetrates and exposes the resist layer R
1
b
which is designed to remain. When the above is developed, the remaining resist layer R
1
b
has a chipped edge, as shown in
FIG. 11
, so that good patterning of the resist layer cannot be obtained.
To overcome the problem described above, in Japanese Unexamined Patent Application Publication No. 8-153704, a technology for disposing an organic antireflection film between a polysilicon layer
126
and a resist layer R
1
is proposed. By disposing the antireflection film mentioned above, exposure light which penetrates the antireflection film is absorbed and does not reflect at an interface between the resist layer and the antireflection film, so that a resist mask having desired dimensions and shapes can be obtained.
However, the organic antireflection film as described above is not removed when the resist mask is formed, and it remains on the polysilicon layer. Hence, for etching the polysilicon layer by using a resist mask, the organic antireflection film is required to be etched in desired dimensions and shapes by using a resist mask.
Accordingly, for forming a gate electrode by the use of an organic antireflection film and a resist mask prepared by a photolithographic method, two etching methods are used. One etching method is to have the organic antireflection film provided with controlled dimensions and shapes by the use of a resist mask; the other etching method is to have the gate electrode provided with controlled dimensions and shapes by the use of the mask composed of the resist and the antireflection film.
SUMMARY
One embodiment relates to a method for manufacturing a semiconductor device including forming a dielectric film on a semiconductor substrate and forming a conductive film containing silicon on the dielectric film. An organic antireflection film is formed on the conductive film and a resist layer having a predetermined pattern is formed on the organic antireflection film. The method also includes etching the organic antireflection film using the resist layer as a mask, using an etching gas that includes at least one of an oxygen-based gas and a chlorine-based gas. A gate electrode is formed by etching the conductive layer with a predetermined pattern.
Another embodiment relates to a method for fabricating a semiconductor device including forming a dielectric film on a semiconductor substrate and a conductive film on the dielectric film. The method also includes forming an organic antireflection film on the conductive film and forming a resist layer having a predetermined pattern on the organic antireflection film. The organic antireflection film is etched using the resist layer as a mask, using an etching gas that includes at least one of an oxygen-based gas and a chlorine-based gas. The conductive layer is etched with a predetermined pattern.
Another embodiment relates to a method for fabricating a semiconductor device including forming a conductive film containing silicon over a dielectric layer and forming an organic antireflection film on the conductive film. A resist layer having a predetermined pattern is formed on the organic antireflection film. The method also includes etching the organic antireflection film using the resist layer as a mask, using an etching gas including an oxygen-based gas and a chlorine-based gas. The method also includes etching conductive layer with a predetermined pattern.


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Ta et al., “A sub-half micron deep-UV integrated ARC process”, Proc. Electrochem. Soc. (1992), 92-18, pp 460-471.*
U.S. Application Serial No. 09/438,166, docket No. 0010-0008, filed Nov. 11, 1999.
Translation of “Notice of Grounds for Rejection” re: Japanese 1999 Patent Application 251217, date of notice Apr. 4, 2001.

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