Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-03-13
2002-03-12
Lee, Eddie (Department: 2845)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S338000, C257S351000, C257S357000, C257S371000, C257S376000
Reexamination Certificate
active
06355962
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to CMOS FET semiconductor memory and logic devices with enhanced ESD (ElectroStatic Discharge) performance and more particularly to the source and drain regions structures therein and methods of manufacture thereof.
2. Description of Related Art
1. The reduced drain doping concentration in deep submicron transistors reduces substrate current, and delays the snapback effect.
2. An ESD deep-drain-implant cannot be used due to significant punchthrough effect between source and drain.
U.S. Pat. No. 5,595,919 of Pan for “Method for Making Self-Aligned Halo Process for Reducing Junction Capacitance” describes an LDD structure made using a self-aligned halo process.
U.S. Pat. No. 5,496,751 of Wei et al. for “Method of Forming an ESD and Hot Carrier Resistant Integrated Circuit Structure” describes a method of forming an ESD circuit having LDD regions (preferably formed by LATID) and DDD regions. Among other things, this reference differs from the counter Halo/drain halo regions of the present invention.
U.S. Pat. No. 5,650,340 of Burr et al. for “Method of Making Asymmetric Low Power MOS Devices” teaches a low threshold voltage MOS devices having asymmetric halo implants. An asymmetric halo implant provides a pocket region (P+) located under the source region or under the drain region of a device.
U.S. Pat. No. 5,534,449 of Dennison et al. for “Methods of Forming Complementary Metal Oxide Semi-conductor CMOS Integrated Circuitry” describes a method of forming CMOS integrated circuitry having four doped regions comprising the source/drain regions.
A problem with the prior art in view of trends to greater degrees of miniaturization is that junction leakage and junction short circuits to the substrate are more and more likely to occur in advanced technology devices as the dimensions of the devices forming those circuits become smaller and smaller.
SUMMARY OF THE INVENTION
An object of this invention is to reduce drain breakdown voltage to increase substrate current, without degrading punchthrough effect.
An object of this invention is to reduce the snapback V
be
at source junction.
A key feature of this invention is a counter doped halo region for the source region with drain halo regions in an ESD transistor.
In accordance with this invention, a method of forming a semiconductor memory device formed on a semiconductor substrate with an N-well and a P-well with source/drain sites in the N-well and in the P-well comprises the following steps. Form a gate oxide layer and a gate electrode layer patterned into a gate electrode over a substrate with N-well and P-well. Form N− LDS and LDD regions in the P-well. Form P− LDS/LDD regions in the N-well and P− lightly doped halo regions in the P-well below the source site N-LDS and the drain site N-LDD in the P-well. Form a counter doped halo region doped with N type dopant below the source region site in the N-well. Form spacers on the gate electrode sidewalls. Thereafter form lightly doped regions self-aligned with the gate electrode in the source/drain sites. Form N+ type doped source/drain regions deeper than the N− LDS/LDD regions in the P-well in the source/drain sites. Form P+ type doped source/drain regions deeper than the P− LDS/LDD regions in the N-well in the source/drain sites.
Preferably, the counter doped N type halo region is formed to a depth from about 400 Å to about 2,500 Å below the surface of the substrate. The counter doped N type halo region is formed to a depth from about 400 Å to about 2,500 Å below the surface of the substrate.
LDD/LDS regions are formed in the P-well by ion implanting with a dose of phosphorus or arsenic dopant ions from about 1 E 13 ions/cm
2
to about 5 E 14 ions/cm
2
at an energy from about 30 keV to about 80 keV.
P type dopant is ion implanted into the P-well on the side of the gate below the N− lightly doped region and ion implanting ions of P type dopant into the N-well comprising boron or boron difluoride (BF
2
) are ion implanted into LDS/LDD regions in the N-well with a dose from about 1 E 13 ions/cm
2
to about 5 E 14 ions/cm
2
at an energy from about 15 keV to about 50 keV. An N− halo region below the source region is formed in the P-well by ion implanting with a dose of phosphorus or arsenic dopant ions from about 1 E 12 ions/cm
2
to about 1 E 14 ions/cm
2
at an energy from about 20 keV to about 80 keV. A P− lightly doped halo region is formed in the P-well below the source site concomitantly with forming the halo region below the drain site.
A semiconductor CMOS memory or logic device is formed on a semiconductor substrate with an N-well and a P-well with source/drain sites in the N-well and in the P-well.
The combination of a gate oxide layer and a gate electrode layer patterned into gate electrode stacks with sidewalls formed over a substrate includes an NMOS FET device over a P-well and a PMOS FET device over an N-well.
P− lightly doped source (LDS) and lightly doped drain (LDD) regions are formed in the N-well. Together with the same implant, a P-halo is formed in the P-well.
N− lightly doped source LDS and LDD regions are formed in the P-well. An N− counter doped implant is implanted in the source side of the P-well, which compensates the P− halo implant, forming a P-type counter doped region. The concentration of the counter doped region
31
is less than the P-well region
16
.
Spacers are formed on the sidewalls of the gate electrode stacks.
There are N+ type source/drain regions in the P-well in the source/drain sites self-aligned with a the gate electrode stack, and P+ type source/drain regions in the N-well in the source/drain sites self-aligned with a the gate electrode stack. There is a P− lightly doped halo region in the P-well below the drain site in the P-well; and a counter doped halo region doped with N type dopant, which compensates the P-halo implant, formed below the source region site in the P-well.
LDS/LDD regions were formed in the P-well by ion implanting with a dose of phosphorus or arsenic dopant ions from about 1 E 13 ions/cm
2
to about 5 E 14 ions/cm
2
at an energy from about 30 keV to about 80 keV, and after annealing the concentration of phosphorus or arsenic dopant in the LDS/LDD regions was from about 5 E 16 atoms/cm
3
to about 1 E 19 atoms/cm
3
.
Ions of P type dopant were implanted into the P-well on the side of the gate below the N− LDD and LDS region and ions of P type dopant implanted into the N-well comprising boron or boron difluoride (BF
2
). The ions were ion implanted into LDS/LDD regions in the N-well with a dose from about 1 E 13 ions/cm
2
to about 5 E 14 ions/cm
2
at an energy from about 15 keV to about 50 keV and after annealing the concentration of boron dopant in the LDD/LDS regions in the N-well and halo regions in the P-well under the drain region and under the source region was from about 5 E 16 atoms/cm
3
to about 1 E 19 atoms/cm
3
. The N− LDD/LDS regions overcompensate the P type halo region dopant.
An N− halo region was formed below the source region in the P-well by ion implanting with a dose of phosphorus or arsenic dopant ions from about 1 E 12 ions/cm
2
to about 1 E 14 ions/cm
2
at an energy from about 20 keV to about 80 keV and after annealing the concentration of phosphorus or arsenic dopant in the counter doped halo region was from about 1 E 16 atoms/cm
3
to about 5 E 18 atoms/cm
3
. This counter doping compensates the P-halo doping, reducing the net concentration so the net dopant is now P-type and the concentration is less than the P-well concentration.
REFERENCES:
patent: 5492847 (1996-02-01), Kao et al.
patent: 5496751 (1996-03-01), Wei et al.
patent: 5534449 (1996-07-01), Dennison et al.
patent: 5595919 (1997-01-01), Pan
patent: 5650340 (1997-07-01), Burr et al.
patent: 5736446 (1998-04-01), Wu
patent: 5917219 (1999-06-01), Nandakumar et al.
patent: 5930615 (1999-07-01), Manning
Liang Mong-song
Wong Shyh-chyi
Ackerman Stephen B.
Jones II Graham S.
Lee Eddie
Taiwan Semiconductor Manufacturing Company
Warren Matthew E.
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