Memory module system having multiple memory modules

Details Memory module system having multiple memory modules Memory module system having multiple memory modules

1998-11-19

2002-01-08

Nguyen, Hiep T. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C710S120000, C713S324000

Reexamination Certificate

active

06338113

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to memory module systems, and more specifically, to a memory module system having a plurality of memory modules.
2. Description of the Background Art
The main memory in a computer system such as personal computer and workstation is supplied on the basis of a memory module including a plurality of memory chips. In recent years, the scale of OS′ or application software in the computer system has much grown, and the size of data has also increased by the introduction of three-dimensional CAD/image data, which greatly accelerates the growth of the scale of the main memory. In order to cope with the development, memory chips are further integrated to increase the capacity per a single memory module, or the number of memory modules connected to a single external data bus is increased.
As the number of memory modules connected to a single external data bus has increased as described above, the load of the external data bus increases as well, which impedes data transfer at a high speed. As a result, the number of memory modules connected to a single external data bus is necessarily limited.
SUMMARY OF THE INVENTION
The present invention is directed to a solution to the above-described problem, and it is an object of the present invention to provide a memory module system that permits high-speed data transfer to be maintained and the capacity of memory modules to be increased.
A memory module system according to the present invention includes a plurality of memory modules, a memory controller, and an external data bus. The memory controller selects any of the memory modules. The external data bus is common to the plurality of memory modules. The plurality of memory modules each include a printed circuit board, a plurality of memory chips, a plurality of internal data buses, and a plurality of first switching elements. The plurality of memory chips are mounted on the printed circuit board. The plurality of internal data buses corresponding to the plurality of memory chips are formed on the printed circuit board and each connected to a corresponding memory chip. The plurality of first switching elements corresponding to the plurality of internal data buses are provided on the printed circuit board and each connected between a corresponding internal data bus and the external data bus. The memory module system further includes a control circuit. The control circuit turns on the plurality of first switching elements in a memory module selected by the memory controller, while turns off the plurality of first switching elements in the memory modules other than the selected memory module.
As a result, only the selected memory module is connected to the external data bus. Thus, increase in the number of memory modules to be connected to the external data bus does not increases the load of the external data bus, which permits high speed data transfer to be maintained and the capacity of the memory modules to be increased.
The control circuit preferably includes a plurality of logic chips. The plurality of logic chips are provided corresponding to the plurality of memory modules, and each mounted on the printed circuit board in a corresponding memory module. The plurality of logic chips each turn on the plurality of first switching elements in a corresponding memory module if the memory controller selects the corresponding memory module, and otherwise turn off the plurality of first switching elements.
In the memory module system described above, since the plurality of logic chips are newly mounted on the printed circuit board in the memory modules, the specification of the existing memory chips does not have to be changed.
The memory controller preferably applies a command signal representing a writing or reading mode to the plurality of logic chips, each of which turns on the plurality of first switching elements in a corresponding memory module after a latency period since the command signal is received, and then turns off the plurality of first switching elements after passage of a burst length period since the plurality of switching elements are turned on.
Thus, time required for writing/reading data to/from a memory chip is equal to the time during which the plurality of first switching elements corresponding to the memory chip are turned on.
The control circuit preferably includes a plurality of logic circuits. The plurality of logic circuits are provided corresponding to a plurality of memory modules, each built inside at least one of a plurality of memory chips in a corresponding memory module, each turn on the plurality of first switching elements in a corresponding memory module when the memory controller selects the corresponding memory module, and otherwise turns off the plurality of first switching elements.
In the memory module system, since logic circuits are newly provided in a memory chip, new logic chips are not necessary on a memory module.
The memory controller preferably applies a command signal representing a writing or reading mode to the plurality of logic circuits, each of which turns on the plurality of first switching elements in a corresponding memory module after a latency period since the command signal is received, and then turns off the plurality of first switching elements after a burst length period since the plurality of first switching elements are turned on.
Thus, time required for writing/reading data to/from a memory chip is equal to the time during which the plurality of first switching elements corresponding to the memory chip are on.
The memory controller preferably applies a command signal representing a writing or reading mode to the plurality of logic circuits. The plurality of logic circuits each include a write driver enable generation circuit, an output enable generation circuit, and an OR circuit. The write driver enable generation circuit generates a write driver enable signal which is activated after a writing latency period since the command signal representing the writing mode is received, and is then inactivated after a burst length period since the activation. The output enable generation circuit generates an output enable signal which is activated after a column address strobe latency period since the command signal representing the reading mode is received, and is then inactivated after a burst length period since the activation. The OR circuit receives the write driver enable signal and the output enable signal. The plurality of first switching elements in each of the memory modules are each a transistor having a gate to receive the output signal of an OR circuit in a corresponding logic circuit.
In the memory module system described above, the command signal representing the writing or reading mode is applied to a plurality of logic circuits included in a memory module selected by the memory controller. In response to the command signal, the plurality of logic circuits apply, to the gate of each of the plurality of transistors, a signal which is activated after a latency period since receiving the command signal representing the writing or reading mode, and is then inactivated after a burst length period since the activation. As a result, during the period in which data is written/read to/from a memory chip, a plurality of transistors corresponding to the memory chip are turned on.
The memory controller preferably applies the command signal representing the writing or reading mode and a data transfer start signal representing the start of data transfer to the control circuit. The control circuit is provided corresponding to the plurality of memory modules, and includes a plurality of first logic circuits and a plurality of second logic circuits. The plurality of first logic circuits are each built in at least one of the plurality of memory chips in a corresponding memory module, and generates a writing/reading end signal representing the end of writing/reading data to/from the plurality of memory chips in response to the command signal re

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