Semiconductor memory device having improved memory cell and...

Details Semiconductor memory device having improved memory cell and... Semiconductor memory device having improved memory cell and...

2001-01-26

2002-04-23

Nelms, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S051000, C365S063000

Reexamination Certificate

active

06377483

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a system LSI mounted with memories.
2. Description of the Background Art
System LSIs have been developed such as a DRAM with a logic in which a logic such as a processor or ASIC (IC for specific purpose) and a dynamic random access memory (DRAM) having a large storage capacity are integrated on the same semiconductor chip (semiconductor substrate). In such a system LSI, connecting a logic and a memory such as a DRAM to each other by an internal data bus of as many as 128 to 512 bits realizes data transfer rate higher than a general-purpose DRAM by one digit or more digits.
The DRAM and the logic are connected by an internal wiring whose length is shorter enough than a board wiring and whose parasitic impedance is small, which enables drastic reduction of charging and discharging currents of the data bus and enables high-speed signal transmission. In addition, because of the connection between the logic and the DRAM by an internal wiring, the number of external pin terminals of the logic can be decreased to be less than that of a system in which a general-purpose DRAM is externally attached to a logic.
For these reasons, system LSIs such as a DRAM with a logic largely contribute improvement in performance of information apparatuses for executing such processing of handling a large volume of data as three-dimensional graphic processing, and image and voice processing.
FIG. 20
is a diagram schematically showing a structure of a conventional DRAM-embedded system LSI
900
. With reference to FIG.
20
. the system LSI
900
includes a large-scale logic LG coupled to an external pin terminal group LPGA for executing processing instructed, an analog core ACR coupled between the large-scale logic LG and an external pin terminal group APG for executing processing with respect to an analog. signal, a DRAM core MCR coupled to the large-scale logic LG through an internal wiring for storing data required by the large-scale logic LG, and a test interface circuit TIC for cutting off the large-scale logic LG and the DRAM core MCR, as well as coupling an external memory tester to the DRAM core MCR through a test pin terminal group TPG at the test mode. The DAM core MCR receives a power supply voltage VCC through a power supply pin terminal PST.
The analog core ACR includes a phase locked loop circuit (PLL) for generating an internal clock signal, an analog-digital converter for converting an external analog signal into a digital signal, and a digital-analog converter for converting a digital signal applied from the large-scale logic LG into an analog signal and outputting the analog signal.
FIG. 21
is a schematic sectional view of a DRAM core MCR and a large-scale logic LG manufactured by the DRAM-logic merging process. With reference to
FIG. 21
, on the surface of a semiconductor substrate
902
, an N channel MOS transistor
906
and a P channel MOS transistor
908
electrically isolated from each other by a trench isolation
904
are formed. A gate electrode layer
910
is made of a material containing, for example, impurity-doped polycrystalline silicon (doped polysilicon) or silicon such as polycide including WSix. An interlayer insulation film
912
is formed over the surface so as to cover the MOS transistors
906
and
908
. On the interlayer insulation film
912
, a bit line layer
914
is formed for forming a bit line in the DRAM core MCR. An interlayer insulation film
916
is formed over the surface so as to cover the bit line layer
914
. On the interlayer insulation film
916
, an interlayer insulation film
918
is formed. On the interlayer insulation film
918
, metal wiring layers
920
to
922
and interlayer insulation films
924
to
926
are formed alternatively. The metal wiring layers
920
to
922
are made of, for example, a metal such as aluminum (Al) or an alloy containing aluminum and copper (Cu). The first metal wiring layer
920
is electrically connected to the bit line layer
914
by a plug
918
b
which is formed by plugging tungsten (W) etc. into a contact hole
918
a.
The second metal wiring layer
921
and the third metal wiring layer
922
are electrically connected to the metal wiring layers
920
and
921
by plugs
924
b
and
925
b
which are formed by plugging tungsten (W) etc. into through holes
924
a
and
925
a,
respectively. In a complete CMOS logic process with no DRAM mounted, the above-described bit line layer
7
(
914
) is unnecessary.
FIG. 22
is a layout diagram showing a schematic structure of a memory cell array in the DRAM core MCR illustrated in
FIG. 20. A
plurality of sub-memory arrays SMA illustrated in
FIG. 22
are disposed in the row direction (horizontal direction in
FIG. 22
) to constitute a sub-block. A plurality of sub-blocks are disposed in the column direction (vertical direction in
FIG. 22
) to constitute the entire memory cell array. The memory cell array has a so-called “hierarchical word line” (also called “divided word line”) structure in which a main word line MWL and a sub-word line SWL are arranged. Also bit line pairs BL, ZBL are arranged to intersect with these sub-word lines SWL. The bit line pair BL, ZBL has a folded bit line structure having a high noise-tolerance. The bit line pair BL, ZBL is connected to a sense amplifier S/A arranged in a sense amplifier band SAB. The sub-word line SWL is connected to a sub-word driver SD arranged in a sub-word driver band SDB.
At a crossover point between the sub-word line SWL and the bit line BL or ZBL, a memory cell MC is formed. Each memory cell MC is made up of an access transistor and a storage capacitor. At two memory cells MC adjacent to each other, the bit line BL or ZBL is connected to two access transistor field regions
932
through a shared bit line contact
930
. At each memory cell MC, a storage node is connected to the field region
932
of the access transistor through a storage node contact
934
. Here, projecting a minimum pitch length of the memory cell MC obtained by obliquely linking the bit line contacts
930
in the bit line direction results in having a length half an arrangement pitch of the memory cell MC in the bit line direction, which memory cell arrangement is referred to as “half-pitch cell” (also called “½ pitch cell”).
FIG. 23
is a schematic sectional view of the sub-memory cell array SMA and the sub-word driver band SDB shown in FIG.
22
. As illustrated in
FIG. 23
, on the surface of the semiconductor substrate
902
, N or P channel MOS transistors
940
and
942
are formed. The transistor
940
forms the access transistor of the memory cell MC and the transistor
942
forms the sub-word driver SD. The sub-word line SWL is formed in the gate layer
910
. The bit line BL and a configuration dummy bit line DBL are formed in the bit line layer
914
. A capacitor
944
of the memory cell MC is formed between the interlayer insulation films
916
and
918
. The capacitor
944
is made up of a storage node
946
and a cell plate electrode
936
. The capacitor
944
is formed over the bit line BL to make a so-called COB (Capacitor Over Bit line) structure. Therefore, the storage node
946
between the adjacent bit lines serves as a shield to further enhance a noise-tolerance. The capacitor
944
is of a stack type for ensuring a capacity and has a complicated three dimensional structure in which the storage node
946
is formed to be a tall cylinder and the surface is made rough although it is not shown in order to further enlarge a capacitor area. As a result, a large step is generated between the memory cell array and the remaining peripheral circuits to make narrowing of a wiring pitch of the metal wiring layers
920
to
922
difficult. Under these circumstances, the above-described step is drastically reduced by the introduction of a planarization process using CMP (Chemical Mechanical Polishing).
Thus, the system LSI with the DRAM further needs, in addition to an ordinary CMOS logic

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