Static information storage and retrieval – Read/write circuit – Having fuse element
Reexamination Certificate
2000-02-25
2002-01-01
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having fuse element
C365S227000, C365S154000
Reexamination Certificate
active
06335891
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to semiconductor memory devices and, more specifically, to devices and methods for reducing standby current in a semiconductor memory device, such as a Static Random Access Memory (SRAM), by disconnecting bit line load devices in unused columns of the memory device from a supply voltage.
2. State of the Art
As shown in
FIG. 1
, a conventional SRAM memory cell
10
is activated for storage of a logic bit when a wordline WL associated with the memory cell
10
goes high and turns on access NMOS transistors
12
and
14
. A logic “0” bit, for example, to be stored in the memory cell
10
is then applied to bit lines BL and BL* as a low on the bit line BL and as a high on the bit line BL*. The high on the bit line BL* passes through the activated access transistor
14
to a storage node B, where it turns on a latching NMOS transistor
16
, causing a current I
BL
to flow through a PMOS transistor bit line load device
18
, down the bit line BL, and through the activated access transistor
12
and the activated latching transistor
16
to ground. At the same time, the low on the bit line BL, and the activated state of the latching transistor
16
, pull a storage node A low, so that another latching NMOS transistor
20
is off. When the wordline WL subsequently goes low and turns off the access transistors
12
and
14
, the storage node A remains low, and the storage node B remains high, so that a logic “0” bit is stored in the memory cell
10
.
Of course, a logic “1” bit may also be stored in the memory cell
10
. In this case, the wordline WL goes high to turn on the access transistors
12
and
14
, and the logic “1” bit is applied to the bit lines BL and BL* as a high on the bit line BL and as a low on the bit line BL*. The high on the bit line BL passes through the activated access transistor
12
to the storage node A, where it turns on the latching transistor
20
, causing a current I
BL*
to flow through another PMOS transistor bit line load device
22
, down the bit line BL*, and through the activated access transistor
14
and the activated latching transistor
20
to ground. At the same time, the low on the bit line BL*, and the activated state of the latching transistor
20
, pull the storage node B low, so that the latching transistor
16
is off. When the wordline WL subsequently goes low and turns off the access transistors
12
and
14
, the storage node B remains low, and the storage node A remains high, so that a logic “1” bit is stored in the memory cell
10
.
Examples of conventional SRAM devices that operate substantially as described above may be found in U.S. Pat. No. 5,521,874 to Sandhu and U.S. Pat. No. 5,276,647 to Matsui et al.
Periodically, SRAM memory cells, such as the memory cell
10
, are found to be defective during manufacturing as a result of fabrication or other manufacturing errors. When this occurs, the rows or columns that contain these defective memory cells are typically switched out of service and replaced by redundant rows or columns. Thus, for example, if the memory cell
10
is found to be defective, its associated column
24
may be switched out of service and replaced by a redundant column
26
. The redundant column
26
typically shares the wordline WL with the switched out column
24
, but has its own bit lines
28
and
30
and associated PMOS transistor bit line load devices
32
and
34
.
During memory operations, the wordline WL goes high when any memory cell attached to the wordline WL, such as a redundant memory cell
36
in the redundant column
26
, is to be activated. Thus, for example, if a data bit is to be written to, or read from, the redundant memory cell
36
, or the redundant memory cell
36
is to be refreshed, the wordline WL goes high.
Because the defective memory cell
10
in the column
24
remains attached to the wordline WL even after the column
24
has been switched out of service, the currents I
BL
and I
BL*
still flow to ground through the memory cell
10
whenever the wordline WL goes high to activate a memory cell. Thus, in standby mode, when memory cells, such as the redundant memory cell
36
, are refreshed, the currents I
BL
and I
BL*
flow to ground at the same time. As a result, these currents add unnecessarily to the standby current flowing during the standby mode. Although the additional standby current caused by a single replaced column is generally insignificant, the size of modern memory devices typically necessitates tens or hundreds of columns being replaced, and the additional standby current caused by these tens or hundreds of replaced columns can be significant and problematic. Indeed, if the additional standby current drawn by these multiple replaced columns causes the total standby current in a memory device to exceed a specified maximum, then the memory device is typically scrapped.
Therefore, there is a need in the art for a device and method for reducing standby current flowing to unused columns in memory devices.
SUMMARY OF THE INVENTION
Inventive bit line load circuitry that eliminates wasted standby current flowing to an unused column in a memory device includes a programmable circuit, such as a fuse or anti-fuse, interposed between one or more bit line load devices in the unused column and the supply voltage. Programming the programmable circuit causes the circuit to isolate the bit line load devices from the supply voltage so the devices draw no current, thus reducing the total standby current of the memory device. The programmable circuit may be programmed by blowing a fuse with a laser or with excessive current, or by blowing an anti-fuse with excessive voltage.
In other embodiments of the present invention, the bit line load circuitry described above is incorporated into a memory device, such as a Static Random Access Memory Device (SRAM), and an electronic system, or is fabricated on the surface of a semiconductor wafer.
In another embodiment of the present invention, a method for reducing standby current in a memory device having unused columns includes isolating bit line load devices of the unused columns from the supply voltage.
In still another embodiment, a method of repairing a defective memory cell in a memory device having a plurality of memory cells arranged in rows and columns includes switching a column of memory cells containing the defective memory cell out of service. A redundant column of memory cells is enabled to replace the switched-out column, and programmable circuitry provided between bit line load devices of the switched-out column and a supply voltage is then programmed to isolate the bit line load devices of the switched-out column from the supply voltage.
REFERENCES:
patent: 4701644 (1987-10-01), Campoine
patent: 4701884 (1987-10-01), Aoki et al.
patent: 5253197 (1993-10-01), Suzuki et al.
patent: 5276647 (1994-01-01), Matsui et al.
patent: 5309401 (1994-05-01), Suzuki et al.
patent: 5521874 (1996-05-01), Sandhu
patent: 5579266 (1996-11-01), Tahara
patent: 6018488 (2000-01-01), Mishima et al.
Auduong Gene N.
Micro)n Technology, Inc.
TraskBritt
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