Static information storage and retrieval – Read/write circuit – Simultaneous operations
Reexamination Certificate
2000-11-27
2002-03-19
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Simultaneous operations
C365S189011, C365S201000
Reexamination Certificate
active
06359811
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, a semiconductor integrated circuit having a RAM built therein, such as, for example, a single chip microcomputer.
2. Description of Related Art
Typically, a RAM built in a semiconductor integrated circuit such as a single chip microcomputer transfers and receives signals to and from a central processing unit through a data bus. In other words, as shown in
FIG. 2
, for example, a RAM has columns or rows of memory cells defining memory cell columns ML
1
, ML
2
. . . MLn that are connected to a data bus DB through input/output control circuits
2
provided for the respective memory cell columns ML
1
, ML
2
. . . MLn. An input/output control circuit
2
is formed from two three-state circuits for writing and reading operations that are connected to one another in mutually inverse directions.
The data bus DB connects to the central processing unit (not shown). Each of the input/output control circuits
2
operates according to a logical sum of a writing command signal WR or a reading command signal RD and an enable signal CE
1
, CE
2
, . . . CEn provided from the central processing unit. The central processing unit controls the enable signals CE
1
, CE
2
. . . CEn, and switches the enable signals CE
1
, CE
2
, . . . CEn set at an “H” level depending on the memory regions to be accessed. When the writing command signal WR is at an “H” level, those of the memory cell columns with the enable signal being at the “H” level become effective, and data from the central processing unit are transferred through the data bus DB and the input/output control circuits
2
and written in designated memory cells in the effective memory cell columns ML
1
, ML
2
. . . MLn. Similarly, when the reading command signal RD is at an “H” level, those of the memory cell columns with the enable signal being at the “H” level become effective, and data stored in designated memory cells are transferred through those of the input/output control circuits
2
corresponding to the effective memory cell columns, and through the data bus DB to the central processing unit.
When the RAM is tested, test data is transferred from the central processing unit through the data bus DB and written in specified addresses in the RAM. Then, for the test of the RAM, the data stored in the specified addresses are read out onto the data bus DB and compared with the test data that is written, to thereby observe the status of the stored data that is read out.
SUMMARY OF THE INVENTION
Since the RAM is accessed through the central processing unit and the data bus DB, the number of the memory cells in which data can be simultaneously written is limited. Similarly, when stored data is read from the memory cell columns ML
1
, ML
2
, . . . MLn, the number of data that can be simultaneously read out is limited.
Although the number of data that can be simultaneously written or read is limited, the user may not feel that the processing time required for such operations is very long. The processing time required for writing or reading data is relatively short compared with the operation time that is spent by the user, and therefore does not make the user feel inconvenient and does not present any problems to the user. However, when operation tests are conducted on semiconductor integrated circuits before shipping, test data are written in all addresses in each of the semiconductor integrated circuits, and then the stored data is read from all of the addresses. Accordingly, the processing time for writing or reading the data is relatively long with respect to the overall test time. In other words, the fact that the number of data that can be simultaneously written or read is limited poses a major obstacle to an effort in shortening the test time.
To avoid such an obstacle, a RAM may be divided into a plurality of blocks. Test data can be simultaneously written in a plurality of addresses. However, when data stored in the RAM is read, the read data may collide with one another on the data bus. Therefore, it is difficult to simultaneously read the stored data.
Therefore, the present invention has been made at least in view of the unsolved problems of the conventional technique, and an object of the present invention is to provide a semiconductor integrated circuit that can readily perform a test on RAMs mounted therein.
A semiconductor integrated circuit according to an exemplary embodiment of the present invention, in which data stored in a storage region is read through a data bus, may consist of a first reading device that is interposed between the storage region and the data bus and that reads out data stored in the storage region, a second reading device that reads out data stored in the storage region independently of the first reading device and that outputs to an individual output terminal provided for the respective stored data, and a switching device that switches in response to a mode-switching signal between reading of the stored data by the first reading device and reading of the stored data by the second reading device.
According to this exemplary embodiment of the present invention, the first reading device is provided between the storage region and the data bus, and stored data is read by the first reading device from the storage region onto the data bus. Furthermore, the second reading device reads out data stored in the storage region independently of the first reading device and outputs the data to each of the individual output terminals provided for the respective stored data. Also, the switching device switches in response to a mode-switching signal between reading of the stored data by the first reading device and reading of the stored data by the second reading device.
In other words, the stored data read out by the second reading device is outputted to each of the individual output terminals provided for the respective stored data. Therefore, for example, the stored data may be read out in the unit of the number of the output terminals. As a result, the stored data can be retrieved in the unit of the number of the output terminals without the plural stored data being collided.
It is noted that, when the stored data is read through the data bus, the number of the data that can be read is limited due to the bit number of the data bus or the like. This does not pose any problems in the normal use of the semiconductor integrated circuit. However, when an operation test is conducted on the semiconductor integrated circuit, test data is written in the storage region, and then the stored data is read from the storage region to observe the stored data. Therefore, it takes a long time for reading the stored data alone.
In this case, the switching device switches from an operation of reading the stored data through the data bus by the first reading device to an operation of reading the stored data by the second reading device, such that a plurality of stored data are read out to the output terminals. As a result, the stored data can be read in the unit of the number of the output terminals, and thus the time required for reading out the stored data can be shortened.
Also, in accordance with another exemplary embodiment, the semiconductor integrated circuit may further consist of an output terminal for outputting a signal that is different from the stored data read out by the second reading device, wherein the output terminal is commonly used for outputting the stored data read out by the second reading device.
In accordance with the present invention set forth this exemplary embodiment, an output terminal provided for outputting a signal that is different from the stored data read out by the second reading device is commonly used for outputting the stored data read out by the second reading device. Accordingly, an independent output terminal does not need to be provided for outputting stored data read by the second reading device.
In another exemplary embodiment in the semiconductor integr
Lam David
Nelms David
Oliff & Berridg,e PLC
Seiko Epson Corporation
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