Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-01-31
2002-07-23
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06425114
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention concerns skew reduction, and particularly relates to reduction of skew in clock signal distribution during integrated circuit (IC) design.
2. Description of the Related Art
During integrated circuit design, it is often desirable that a certain signal reaches a number of different components at the same time, or at least as close to the same time as possible. The difference between the maximum delay and the minimum delay for a signal to reach different components is known as “skew”. The difference between the maximum delay and the minimum delay for a signal to reach all components to which it is supplied is referred to as “global skew”.
Controlling skew is particularly important in the design of synchronous digital circuits. Typically, with respect to such circuits, this consideration is most critical for the clock signal, partly because the clock signal is so widely distributed over the surface of the integrated circuit and also because clock skew often will directly influence the maximum speed at which the integrated circuit can operate.
Integrated Circuit Basics
An integrated circuit chip (or die) includes electronic components formed on a surface of a semiconductor substrate and also includes connections between those components.
A cell is a group of one or more circuit elements such as transistors, capacitors, and other basic circuit elements grouped to perform a function. Each of the cells of an IC may have one or more input or output ports (pins). Each such pin, in turn, may be connected to one or more pins of other cells on the IC by electrically conductive traces (or wires). The wires connecting the pins of the IC typically are formed on the metal layers of the chip, which in turn are formed on top of the chip's semiconductor substrate.
A net is a set of two or more pins which are to be connected, thus connecting the logic circuits having the pins. Because a typical chip has thousands, tens of thousands, or hundreds of thousands of pins that must be connected in various combinations, the chip generally also includes definitions of thousands, tens of thousands, or hundreds of thousands of nets, or sets of pins. The number of the nets for a chip is typically on the same order as the order of the number of cells on the chip. Commonly, a majority of the nets include only two pins to be connected; however, many nets include three or more pins. Some nets may include hundreds, thousands or tens of thousands of pins to be connected. A netlist is a list of nets including names of connected pins or a list of cells including names of nets that connect to pins of cells.
The clock signal often is distributed to around 100,000 or more pins. As noted below, because a significant number of buffers typically is required in connection with such distribution, technically speaking clock signal distribution often involves many different nets. Nevertheless, the network for distributing the clock signal is sometimes referred to as the clock net.
Reduction of Clock Signal Skew
Due to the complexity of the clock signal distribution network, it is often very difficult to precisely control the amount of clock skew throughout the IC. Specifically, clock skew typically will be affected by a number of factors, including wire delays, component delays, existence and placement of buffers, and the configuration of the clock net. For example, in order to efficiently distribute the clock signal throughout the IC, it is common to configure the clock signal distribution network as a hierarchical tree, beginning with a single root node that distributes the signal to multiple nodes at the next lower level, each in turn distributing the signal to multiple nodes at the next lower level, and so on, until the signal reaches the actual components (i.e., the leaves of the tree) at the bottom level of the structure. As a result of implementing the clock signal distribution network in this fashion, the delay interrelationships often become even more complicated, making analysis and control of clock skew even more difficult.
In order to maintain the strength of the clock signal as it is distributed throughout the IC, it is common to use buffers. For instance, in the tree-shaped distribution network described above it is common to use a buffer at each node of the tree. In addition to maintaining signal strength, the parameters of these buffers often will affect the amount of delay. Generally, higher drive strength buffers will reduce downstream delay more than lower drive strength buffers. However, due to the complexity of the timing interactions in the typical clock signal distribution network, conventionally it has been very difficult to control buffer parameters so as to achieve an optimal or near optimal result.
While it is theoretically possible to perform an exhaustive search over all possible combinations of buffers in a given configuration, such a search generally will be impractical. Accordingly, prior to the present invention it was common for experienced circuit designers to manually replace individual buffers, according to their best judgment, in an attempt to reduce global skew. However, this approach often was time-consuming, provided inconsistent results and relied heavily on the experience of the individual designer. What has long been needed, therefore, is a more systematic technique for reducing skew.
SUMMARY OF THE INVENTION
The present invention addresses the foregoing problems by systematically aligning delay ranges at different levels of a tree-shaped distribution network.
Thus, in one aspect the invention is directed to skew reduction in a tree-shaped distribution network having plural levels and plural nodes at each level, where a node at one level connects to plural nodes at the next lower level. Initially, the current level is set to the bottom level of the network. Delay ranges are then obtained corresponding to nodes at the current level and the delay ranges are shifted in an attempt to align delay ranges corresponding to nodes at the current level that connect to the same node at the next higher level. These steps are then repeated for all levels in order from the bottom level to the top level.
In a further aspect, the invention is directed to skew reduction in a tree-shaped distribution network having plural levels and plural nodes at each level, where a node at one level connects to plural nodes at the next lower level. Initially, the current level is set to the bottom level of the network. Delay ranges are then obtained corresponding to nodes at the current level and are shifted in an attempt to align delay ranges corresponding to nodes at the current level that connect to the same node at the next higher level. The foregoing steps are then repeated for plural nodes (preferably, all nodes) at the next higher level. Finally, all of the foregoing steps are repeated for all levels in order from the bottom level to the top level.
By aligning delay ranges in the foregoing manner, the present invention often can achieve a significant reduction in skew in a relatively short amount of time and without requiring the user to have any special expertise.
The foregoing summary is intended merely to provide a brief description of the general nature of the invention. A more complete understanding of the invention can be obtained by referring to the claims and the following detailed description of the preferred embodiments in connection with the accompanying figures.
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Vittal et al, “Low-Power Buffered Clock Tree Design,” IEEE, Sep. 1997, pp. 965-975.*
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Kourtev et al, “Synthesis Of Clock Tree Topologies To Implement Nonzero Clock Skew Schedule,” IEEE, Dec. 1999, pp. 321-326.*
Ryoo et al, “Skew Optimization By Combinin
Chan Chun
Yi Bing
LSI Logic Corporation
Mitchell Silberberg & Knupp LLP
Siek Vuthe
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