Insulating gate type semiconductor device

Details Insulating gate type semiconductor device Insulating gate type semiconductor device

1999-05-19

2002-05-21

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S330000, C257S331000, C257S342000, C438S259000, C438S270000, C438S271000, C438S589000

Reexamination Certificate

active

06392272

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to an insulating gate type semiconductor device, and more particularly to a trench gate type IEGT (Injection Enhanced Gate Transistor).
FIG. 1
is a plan view showing a trench gate type IEGT.
The trench gate type IEGT shown in
FIG. 1
is structured such that a gate pad
52
and five element regions
54
are disposed within a terminal region
51
provided along a substrate peripheral region for obtaining a withstand voltage. Gate wires
53
are provided at boundaries of the terminal region
51
, the gate pad
52
and the five element regions
54
. The trench gate type IEGT has striped trench gate electrodes
6
extending as shown in FIG.
1
and disposed inwardly of each element region
54
. A voltage applied to the gate pad
52
is transferred to the trench gate electrode
6
through the gate wire
53
.
A conventional trench gate type IEGT will hereinafter be described.
FIG. 2
is a sectional view taken along the line A-A′ perpendicular to the trench gate electrode
6
of the trench gate type IEGT shown in
FIG. 1
, showing a structure of a first section of the prior art trench gate type IEGT.
The first section of the prior art trench gate type IEGT shown in
FIG. 2
has a structure which follows. An N-type base layer
1
and a P-type base layer
3
are provided in sequence on a P-type emitter layer
2
. Striped trenches for forming the trench gate electrode
6
are arranged substantially in parallel and each recessed extending from the substrate surface through the P-type base layer down to an upper portion of the N-type base layer
1
, and a gate oxide layer
5
is provided over the substrate surface and a trench internal surface. A trench gate electrode
6
defined as a gate electrode composed of polysilicon with a resistance reduced is provided in an interior of the trench covered with the gate oxide layer
5
.
Each set of trench gate electrodes
6
is constituted by fours arranged in sequence in the trench gate type IEGT in the first embodiment of the present invention. Among the four trench gate electrodes
6
constituting one set, the two electrode disposed at both side ends are classified as channel-forming trench gates
6
a,
and remaining two electrodes interposed therebetween are classified as thinning-out trench gates
6
b.
An N-type emitter layer
4
is provided in the vicinity of the channel forming trench gate electrode
6
a
as well as on the substrate surface of the P-type base layer
3
interposed between the channel forming trench gate electrode
6
a
belonging to one set of electrodes and the channel-forming trench gate electrode
6
a
belonging to another set of electrodes adjacent to the above one set of electrodes.
An insulating oxide layer
7
is formed covering some portions or the whole of the upper surfaces of the channel-forming trench gates
6
a
and the gate oxide layers
5
on the substrate surface. A contact hole
10
is holed in the insulating oxide layer
7
and the gate oxide layer
5
at the center of an inter-trench area formed with the N-type emitter layer
4
. An emitter electrode
8
is provided over the entire surface of the substrate surface, covering all these layers and hole described above. Moreover, a collector electrode
9
is provided covering the entire surface of the P-type emitter layer
2
on the underside of the substrate. Accordingly, the emitter electrode
8
is connected at the contact hole
10
to the N-type emitter layer
4
and the P-type base layer
3
.
In the trench gate type IEGT, the contact on the side of the emitter is not formed in all the inter-trench areas. In the case of the prior art trench gate type IEGT shown in
FIG. 2
, there is provided the contact region in which the single contact hole
10
is holed for every four inter-trench areas, and therefore a ratio of the total number of inter-trench areas to the number of the contact regions is 4:1.
The thinning-out trench gate electrode
6
b,
though not used for forming a channel, performs a role of preventing a decrease in element withstand voltage with such a contrivance that when in a forward voltage application, a depletion layer formed extending to a portion peripheral to a tip of the channel-forming trench gate electrode
6
a
is fused with a depletion layer formed extending to a portion peripheral to a tip of the thinning-out trench gate electrode
6
b
adjacent to the channel-forming trench gate electrode
6
a,
and a curvature of the depletion layer at the portion peripheral to the tip of the channel-forming trench gate electrode
6
a
is relieved. Accordingly, if the thinning-out trench gate electrode
6
b
is not provided, the element withstand voltage is to decrease.
FIG. 3
is a sectional view showing a structure of a second section of the trench gate type IEGT in the prior art, i.e., a sectional structure taken along the straight line B-B′ intersecting a direction parallel to the trench gate electrode
6
b
with respect to the gate wire
53
of the trench gate type IEGT shown in FIG.
1
.
The second section of the prior art trench gate type IEGT shown in
FIG. 3
takes the following structure. The N-type base layer
1
is provided on the P-type emitter layer
2
, and a P
+
layer
13
is formed on the N-type base layer
1
at a portion under the gate wire
53
shown in FIG.
1
. An insulating oxide layer
14
is provided on the gate wire region on the P
+
layer
13
. The trenches are formed on both sides of the P
+
layer
13
, and the gate oxide layer
5
is provided covering these components. The trench gate electrode
6
composed of the polysilicon is provided inwardly of the trench covered with the gate oxide layer
5
. A trench gate drawing region
6
′ composed of the polysilicon as in the same way with the trench gate electrode
6
, is provided covering side ends of the trench gate electrode
6
on the side of the P
+
layer
13
, and an area of the gate oxide layer
5
which exists on the insulating oxide layer
14
and the P
+
layer
13
. The trench gate drawing region
6
′ is connected to the side ends of the trench gate electrode
6
on the side of the P
+
layer
13
, whereby the trench gate electrode
6
is drawn out to the gate wire
53
and thus connected to the gate wire
53
. The insulating oxide layer
7
is provided on the trench gate drawing region
6
′, and the gate wire region of the insulating oxide layer
7
is removed. A gate-wire-oriented metal
15
for reducing a resistance is provided on the trench gate drawing region
6
′ from above the insulating oxide layer
7
with the gate wire region removed. The gate wire
53
is constructed of the gate wire-oriented metal
15
and the trench gate drawing region
6
′. The emitter electrode
8
is provided on a region of the insulating oxide layer
7
, wherein the trench gate electrode
6
is formed.
FIG. 4
is a plan view showing, in a region C in
FIG. 1
, the prior art trench gate type IEGT. Note that
FIG. 2
is a sectional structural view taken along the straight line A-A′ perpendicular to the trench gate electrodes
6
(
6
a
and
6
b
) shown in FIG.
4
.
As illustrated in
FIG. 4
, the trench gate electrodes
6
a,
6
b
are formed in a stripe shape alternately at a predetermined interval, and arranged in sequence by fours as one set. Among one set of four trench gate electrodes
6
, two electrodes disposed at both side ends are classified as the channel forming trench gate electrodes
6
a,
and the remaining two electrodes interposed therebetween are classified as the thinning-out trench gate electrodes
6
b.
The insulating oxide layer
7
(not shown in
FIG. 4
) in
FIG. 2
or
3
is formed covering some portions or the whole of the upper surfaces of the trench gates
6
a,
6
b.
The contact hole
10
is holed in an area interposed between the channel-forming trench gate electrode
6
a
belonging to one set of electrodes and the channel-forming trench gate electrode
6
a
belonging to another set of electrodes adjacent t

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