Semiconductor memory

Details Semiconductor memory Semiconductor memory

2001-01-10

2002-07-30

Booth, Richard (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S321000, C438S264000, C438S593000

Reexamination Certificate

active

06426529

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory.
2. Description of the Related Art
The flash memory has a simple construction of memory cell that is suited to packaging with a high density with lower cost per bit, and allows it to write, read and erase data electrically. Thus demand for the flash memory has been increasing and is expected to increase further.
While semiconductor memory devices comprising flash memory cells are required to have higher writing speed as the demand therefor increases, the requirement is not fully satisfied at present.
SUMMARY OF THE INVENTION
Thus an object of the present invention is to provide a semiconductor memory device comprising flash memory cells having higher writing speed.
In order to achieve the object described above, a first semiconductor memory according to the present invention comprises memory cells each having a channel region, an n-type drain region and an n-type source region that are disposed on both sides of the channel region, a floating gate formed over the channel region via a first oxide film and a control gate formed over the floating gate via a second oxide film, which are formed on a p-type Si substrate, wherein the floating gate includes a first region located over the channel region via the first oxide film and a second region that is formed to be wider than the first region and is capacitively coupled with the control gate via the second oxide film, the floating gate having T-shaped longitudinal section, wherein a height of the first region is set so that the floating gate has the maximum potential when a control voltage is applied to the control gate. As a result, the amount of electrons transported to the floating gate can be increased and the writing speed on each memory cell can be increased.
Thus according to the first semiconductor memory of the present invention, a semiconductor memory comprising flash memory cells having higher writing speed can be provided.
A second semiconductor memory according to the present invention comprises memory cells each having a channel region, an n-type drain region and an n-type source region that are disposed on both sides of the channel region, a floating gate formed over the channel region via a first oxide film and a control gate formed over the floating gate via a second oxide film, which are formed on a p-type Si substrate, wherein the floating gate includes a first region located over the channel region via the first oxide film and a second region that is formed to be wider than the first region and is capacitively coupled with the control gate via the second oxide film, the floating gate having T-shaped longitudinal section, wherein a height of the first region is set so as to obtain maximum coupling ratio, which is the ratio of the electrostatic capacitance between the control gate and the floating gate to the electrostatic capacitance of the entire memory cell formed between the control gate and the Si substrate in each memory cell.
Potential of the floating gate can also be maximized with such a constitution as described above.
The electrostatic capacitance of the entire memory cell formed between the control gate and the p-type Si substrate refers to the electrostatic capacitance formed between the control gate and the Si substrate in a single memory cell, and includes the electrostatic capacitance between the control gate and the floating gate, the electrostatic capacitance between the first region and the channel region, the electrostatic capacitance between the second region and the source region, the electrostatic capacitance between the second region and the drain region, the electrostatic capacitance between a side face of the first region and the source region, and the electrostatic capacitance between a side face of the first region and the drain region.
With this configuration, a potential of the floating gate can be made higher and the amount of electrons transported to the floating gate can be increased.
Therefore, according to the second semiconductor memory of the present invention, since the writing speed at each memory cell can be made higher, a semiconductor memory comprising flash memory cells having higher writing speed can be provided.


REFERENCES:
patent: 4823175 (1989-04-01), Fontana
“A 1.28&mgr;m2Contactless Memory Cell Technology for a 3V-Only 64Mbit EEPROM,” by Kume et al., IEDM 92, pp. 991-993.
“A 0.4&mgr;m2Self-Aligned Contactless Memory Cell Technology Suitable for 256-Mbit Flash Memories,” by Kato et al., IEDM 94, pp. 921-923.

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