Semiconductor TFT, producing method thereof, semiconductor...

Details Semiconductor TFT, producing method thereof, semiconductor... Semiconductor TFT, producing method thereof, semiconductor...

1999-11-24

2002-03-26

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S203000, C438S303000, C438S304000

Reexamination Certificate

active

06362031

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor thin film transistor, a producing method thereof, a semiconductor thin film transistor array substrate and a liquid crystal display using the semiconductor thin film transistor array substrate.
More particularly, the present invention relates to an improvement in electric characteristics of a thin film transistor, especially of a thin film transistor that is used in an active matrix type liquid crystal display, and the improvements in electric characteristics particularly being a decrease in serial resistance, a decrease in light generated current when light is irradiated, and a decrease in OFF current.
Switching elements, so-called thin film transistors (hereinafter referred to as “TFT”), that are used in active matrix type liquid crystal displays are classified, depending on the arrangement thereof, as to be either of direct stagger or inverted stagger structure. TFTs of inverted stagger structure are further classified into etching-stopper type TFT (ES-TFT) and channel etch type TFT (“CE-TFT”). FIG.
21
(
a
) and FIG.
21
(
b
) are sectional, explanatory view showing a conventional channel etch type TFT, and FIG.
21
(
a
) is a sectional view showing an arrangement of an etching stopper type TFT (“ES-TFT”) and FIG.
21
(
b
) of a channel etch type TFT (CE-TFT). In FIG.
21
(
a
)and FIG.
21
(
b
),
201
denotes a gate electrode,
202
a gate insulating film,
207
a
and
207
b
a source electrode of two-layer structure,
207
c
and
207
d
a drain electrode of two-layer structure,
209
a
a channel region,
213
an etching stopper film,
214
an amorphous silicon film doped to be of n-type,
221
an insulating substrate, and
223
a channel layer, respectively.
All types of TFTs have an advantage as well as a disadvantage. For instance, since an interface between an etching stopper and an amorphous silicon layer is purely formed in an ES-TFT, characteristics of small OFF current can be obtained. However, on the other hand, it is disadvantaged in terms of small-sizing, since a patterning size of the etching stopper and separation of source electrode and drain electrode running on the etching stopper are prescribed by a transferring accuracy of a transferring device (stepper) so that small-sizing is made difficult, and further, the asymmetrical arrangement of the source electrode and the drain electrode with respect to the etching stopper may result in asymmetric characteristics. To be of asymmetric characteristics means that current-voltage current characteristics differ when the source electrodes is made to be a grounded electrode and when the drain electrode is made to be the grounded electrode. Comparing with this, a CE-TFT is advantageous when comparing with an ES-TFT since small-sizing thereof can be easily performed and the characteristics thereof are not made asymmetric; however, since separation of the source electrode and the drain electrode is performed by etching a channel region of an amorphous silicon layer in which current is supplied, an etching damage exists in the channel region whereby an increase in off current originating therein is observed. Further, the etching of the channel region necessarily results in a thick layer in order to prevent vanishing of the amorphous silicon layer in the channel region due to overetching. Such a thick layer presents such a drawback that it results in an increase in serial resistance in an area between the source electrode to the channel region and an increase in light generated current. With such a background being present, ES-TFT and CE-TFT are coexisting for structures of TFTs used in an active matrix type liquid crystal device.
It will now be explained for a conventional producing method of a CE-TFT (prior art 1) in details with reference to the drawings. FIG.
22
(
a
) to FIG.
22
(
c
) and FIG.
23
(
a
) to FIG.
23
(
c
) are a sectional, explanatory diagram showing each of the processes for producing a conventional CE-TFT. A process flow will now be explained based on FIG.
22
(
a
) to FIG.
22
(
c
) and FIG.
23
(
a
) to FIG.
23
(
c
). First, a Cr film of approximately 300 nm which is to be a gate electrode
201
is deposited onto an insulating substrate
221
made of glass or the like by sputtering method. This is shown in FIG.
22
(
a
). Next, continuous film forming is performed by forming a silicon nitride film (SiNx) as a gate insulating film
202
, an amorphous silicon layer, and an amorphous silicon layer doped to be n-type (n-type amorphous silicon layer)
214
as a channel layer
223
through plasma Chemical Vapor Deposition (CVD). The thickness of the gate insulating layer
202
is 300 to 400 nm, that of the amorphous silicon layer 200 to 400 nm, and that of the amorphous silicon layer doped to a n-type
214
(n-type amorphous silicon layer) 50 to 100 nm. This is shown in FIG.
22
(
b
). Then, the amorphous silicon layer which is to be the channel layer and the n-type amorphous silicon layer
214
are patterned in a shape of an island through dry etching. This is shown in FIG.
22
(
c
). Thereafter, source electrode
207
a
,
207
b
, and drain electrode
207
c
,
207
d
are formed by successively disposing Cr and Al in this order as a two-layer arrangement through sputtering, by patterning through photolithography, and by removing the Cr film and the A
1
film from the channel region
209
through etching. This is shown in FIG.
23
(
a
). Next, etching through dry etching is performed to completely remove etching residues on a region between the source electrode and drain electrode, that is, on the n-type amorphous silicon layer
214
of the channel region
209
. At this time, a part of the amorphous silicon layer of the channel region is also etched by overetching. The amount of overetching is 50 to 100 nm. A diagram of this process is shown in FIG.
23
(
b
). Lastly, a passivation film
210
is formed of silicon nitride film to obtain a channel each type TFT (CE-TFT). This is shown in FIG.
23
(
c
).
When applying a channel etch TFT (CE-TFT) to an active matrix type liquid crystal display to improve the display characteristic thereof, the following mutually related characteristics are required to be improved by decreasing the thickness of the amorphous silicon layer that is to be the channel layer. These characteristics are (1) a decrease in serial resistance, (2) a decrease in light generated current, (3) a decrease in off current originated in junction, and (4) a decrease in off current originated in back channel interface. Each of these will now be explained in detail.
(1) Decrease in serial resistance will first be explained. As shown in the process flow of the prior art, CE-TFT requires an overetching process to completely remove residues of amorphous silicon doped to be n-type that exist between the source electrode and the drain electrode (hereinafter referred to as “between the source and the drain”) after forming the source electrode and the drain electrode. If the residue remains without being removed, it may cause inconveniences in that the n-type amorphous silicon layer residue of low resistance may cause a short-circuit between the source and the drain or in that a silicide film formed by the amorphous silicon and Cr may cause a short-circuit between the source and the drain. Since the selective ratio of the etching for the n-type amorphous silicon layer and the amorphous silicon layer that is to be the channel region is small, the amorphous silicon layer that is to be the channel region is also etched by overetching. In order to prevent a cut between the source and the drain due to overetching, the film thickness of the amorphous silicon layer that is to be the channel region needs to be thick so that the thickness of the amorphous silicon layer which was of approximately 100 nm in an ES-TFT needs to be 200 to 400 nm in CE-TFT. Since the amorphous silicon layer that is to be the channel region is not doped and thus becomes to be a layer of high resistance, it greatly influences the TFT characteristics so that no

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