Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
1999-07-16
2002-07-09
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S775000, C257S765000
Reexamination Certificate
active
06417572
ABSTRACT:
FIELD OF THE INVENTION
The present invention is generally related to semiconductor devices and, more particularly, to the design of metal contacts and interconnections for semiconductor integrated circuits which reduce passivation cracking and extrusion-short failure caused by electromigration. The invention also relates to providing various processes for obtaining the designed structure.
BACKGROUND OF THE INVENTION
Integrated Circuits (IC) typically incorporate and rely on aluminum (Al) based interconnections to carry current to and from active devices (i.e., MOSFETS and Bipolar Transistors). Interconnections of copper (Cu) and gold (Au) have also been used and continue to be used for a limited number of applications. The reliability of these interconnections is generally limited by a phenomenon known as electromigration. Electromigration is the motion of metal atoms in a conductor due to the passage of current. It is basically a diffusion phenomenon in which metal ions and vacancies diffuse in opposite directions with the applied electric field appearing to act as the driving force.
Aluminum-based thin-film metallizations, which are widely used to form conductor patterns and silicate integrated circuits, are especially susceptible to failure caused by electromigration. Electromigration can lead to failure in these devices primarily by one of two failure mechanisms. In both mechanisms, diffusion of the interconnect metal occurs along grain boundaries to cause a net amount of aluminum to migrate in the direction of the electron flow. In the first failure mechanism, aluminum diffuses away from a region in the interconnect faster than the availability of additional atoms can take its place. This forms vacancies. The diffusion of aluminum typically occurs from certain regions, often points where three grains touch, to create vacancies which coalesce at points of flux divergence. As a result, voids are left behind at the negative end of the interconnection. With continued aluminum mass transport, the void grows until a failure occurs, in the interconnection, known as a void-open failure. Although a resistance increase is usually observed in multi-layered metallizations before catastrophic failure occurs, single-layered metallizations may show little or no resistance increase before failing catastrophically.
The second mechanism, by which electromigration failure occurs, is caused by the electromigration of metal atoms into a region faster than the atoms escape the region which creates a local pile-up of metal atoms downstream of the electron flow to form hillocks at the positive end of the interconnection. In confined metal interconnects, such as those deposited on an oxidized silicon substrate and covered by a dielectric passivation layer, the accumulation of metal atoms due to continued mass transport exerts pressure on surrounding insulator layers which are contiguous to the interconnect. As the pressure increases due to continued mass transport, cracks form in the insulator into which aluminum can extrude. Short circuit failures, known as extrusion-short failures, occur when the extruded material extends and contacts adjacent interconnection lines to cause electrical short circuits. As microelectronics circuits are made more dense in order to improve performance, the electric fields (and resulting current densities) in the aluminum interconnects increase. Hence, as circuit densities increase, the rate of electromigration also increases.
The points of flux divergence at which void-open electromigration failures are known to occur (and from which, in single-layer metallization structures, corresponding extrusion-short failures result) vary according to the microstructure and morphology of the wiring structure. In thin-film conductors, flux divergences may be caused by non-uniform structures (e.g., discontinuities such as grain boundaries, variation in grain size, and variation in grain orientation) and non-uniform operating temperatures. Prior art efforts at reducing the probability of electromigration failures for a given time, temperature, and current typically include fabricating conducting interconnects which attempt to reduce flux divergence by eliminating structural non-uniformities.
For wiring structures having single-layer metallization interconnections, flux divergences in the metallization conductors commonly occur at discontinuities of grain structures. U.S. Pat. No. 4,438,450 issued to Sheng et al., U.S. Pat. No. 5,101,261 issued to Maeda, and U.S. Pat. No. 5,382,831 issued to Atakov et al., all attempt to reduce the diffusion flux in single-layer metallization interconnection structures by creating a plurality of narrow interconnect conductors for an integrated circuit in place of a single, wider conductor. The plurality of narrow interconnect conductors are provided in widths comparable to the grain size of the metal interconnect to produce a morphology commonly referred to as a “bamboo microstructure.” In this manner, the metal grains which extend from top to bottom of the conductor and from one side to the other side of the conductor act as blocking grains to prevent the formation of a continuous path of grain boundaries along the length of the patterned conductor.
As a result, the mass transport of the interconnect metal atoms is retarded which in turn slows the formation of voids and minimizes the associated resistance increase. In turn, because the mass transport of interconnect metal atoms is retarded, the incidence of extrusion-short failures is also reduced by blocking grains in single-layer metallization interconnects because the source of atoms which flow downstream of the current flow is reduced. Thus, by replacing a wide-line interconnect (i.e., an interconnect having widths greater than 1 to 1.5 times the mean grain size) with narrow-line interconnects (i.e., interconnects having widths less than 1 to 1.5 times the mean grain size), the atomic flux due to electromigration along the line is reduced. From this replacement it follows that the integrated circuits containing single-layer metallization interconnects are less likely to fail from electromigration, both from void-open and extrusion-short failures, during operation.
Progress toward device scaling of integrated circuits, however, requires increasing the numbers of wiring levels, defined with greater precision, density, and yield. As noted by Hu et al, “Electromigration in Al(Cu) two-level structures: Effect of Cu and kinetics of damage formation,” J. Appl. Phys. 74 (2), pp. 969-978 (1993), the problem of electromigration increases for multi-level interconnect structures because narrower line widths lead to higher current densities. In devices having multi-level wiring levels, however, additional flux divergences may also occur at interfaces between the conductor lines caused by structural non-uniformities such as diffusion barriers between the metallization interconnect layers. Diffusion barriers are particularly are a problem in multi-level structures such as Very Large Scale Integration (VLSI) or Ultra Large Scale Integration (ULSI) devices in which the metallization layers are typically connected by tungsten interlevel connection studs. Because the interlevel connection studs hinder diffusion between various wiring levels, replenishment of depleted metal atoms is prevented, eliminating what is known as the “reservoir effect.” As a result, voids form upstream of the electron flow in the vicinity of the stud which can lead to a void-open failure thereby decreasing the electromigration lifetime of metal interconnections.
In multilevel wiring structures, the current density near the interfaces between conductor lines may increase due to current crowding. U.S. Pat. No. 5,461,260 issued to Varker et al., attempts to reduce the peak localized interconnect current density by creating a plurality of narrow interconnect conductors near the interlevel contact. It should be understood, however, that Varker et al., disclose a structure where current flows through this structure out of the interconnect and
Chidambarrao Dureseti
Filippi Ronald G.
Rosenberg Robert
Shaw Thomas M.
Sullivan Timothy D.
Cao Phat X.
Ratner & Prestia
Townsend, Esq. Tiffany L.
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