Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-06-24
2002-03-19
Pham, Long (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S775000
Reexamination Certificate
active
06359301
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device such as a dynamic random access memory (DRAM) and a method of manufacturing the same, more specifically relates to a semiconductor device comprising transistors formed on a semiconductor substrate and so forth to which bit lines and storage nodes of capacitors are connected via connecting plugs and a method of manufacturing the same.
2. Description of the Related Art
FIG. 26
is a plan view of DRAM cells (four cells) of the related art.
Active regions defined by local-oxidation-of-silicon (LOCOS) regions are arranged alternately in oblique S-shapes. Word lines WL serving also as gate electrodes of selection transistors STr are arranged parallel to each other. Bit contacts BC are located in one of the impurity regions (middle portions of active regions) forming the sources or drains of the selection transistors STr. Bit lines BL connected to the selection transistors through the bit contacts BC are arranged parallel to each other intersecting the word lines WL at right angles. The other of the impurity regions (near the two end portions of the selection transistors of the active regions) are provided with node contacts NC for connection to not illustrated capacitors.
FIG. 27
is a sectional view along the line A-A′ of
FIG. 26
, while
FIG. 28
is a sectional view along the line B-B′ of FIG.
28
. In
FIG. 28
, the left side shows a memory cell area, while the right side shows the peripheral circuit area.
As will be understood from these sectional views, a bit contact BC is comprised of a connecting plug which projects up from one of the impurity regions of the selection transistor and which partially flares outward directly under the bit line BL. Further, the node contact NC also partially flares outward at the same height and connects the other of the impurity regions of the lower layer selection transistor STr and the upper layer capacitor storage node (lower electrode). In this type of DRAM, the bit line is formed in the middle of inter-layer insulating layers in which the connection plug is buried, therefore this type of DRAM is called a “capacitor-over-bit-line” (COB) type.
Next, a simple explanation will be given of the method of manufacture of a COB type DRAM of the related art by referring to
FIG. 29
to FIG.
41
.
First, as shown in
FIG. 29
, a prepared p-type silicon substrate is formed with an n-type well and p-type well and then formed with an element isolation insulating film
201
by ordinary methods. Next, a not illustrated gate insulating film is formed by the thermal oxidation method. After this, a polycrystalline silicon layer doped with impurities to make it conductive (hereinafter referred to as a “doped polycrystalline silicon layer”)
301
a
and a tungsten silicide (WSix) layer
301
b
are stacked on this, then patterned to form a gate electrode
301
(including a word line WL of a selection transistor STr). Ion-implantation is then performed using this gate electrode
301
and the element isolation insulating film
201
as a mask to form on the surface of the well a lightly doped drain (LDD) which has a relatively low concentration of the impurity.
In the step shown in
FIG. 30
, a thin silicon oxide film
202
is formed over the entire surface for use as an etching stopper. Polycrystalline silicon is then deposited and etched back to form a side wall
302
comprised of polycrystalline silicon on the side face of the gate electrode. Ion implantation is then performed using this side wall
302
and the element isolating insulating film
201
as a self-alignment mask to form a source or drain region
102
doped in a relatively high impurity concentration.
The side wall
302
is removed, then, as shown in
FIG. 31
, a silicon nitride film
203
is formed over the entire surface for use as an etching stopper by low-pressure chemical vapor deposition (LP-CVD). Next, a nondoped natural silicate glass (NSG) film
204
is formed by CVD using oxidation of tetraethyloxysilane or tetraethylorthosilicate (Si(OC
2
H
5
)
4
, abbreviated as TEOS) by ozone (hereinafter referred to as the “O
3
-TEOS method”). Next, a borophosphosilicate glass (BPSG) film
205
is formed by the same O
3
-TEOS method.
As shown in
FIG. 32
, the BPSG film
205
is made to reflow to flatten it, a polycrystalline silicon film
303
is deposited, then a photoresist pattern R
11
is formed for forming the apertures for the bit contacts and the node contacts.
As shown in
FIG. 33
, the polycrystalline silicon film
303
, the BPSG film
205
, and the NSG film
204
are successively etched using the photoresist pattern R
11
formed is used as a mask. This etching is stopped midway in the NSG film
204
to form a preparatory contact hole. A polycrystalline silicon film is deposited over the entire surface, then etched back so as to form a side wall
304
made of polycrystalline silicon on the side face of the preparatory contact hole. As a result, the diameter of the preparatory contact hole is reduced. Next, the NSG film
20
remaining underneath is etched using this side wall
304
and the polycrystalline silicon film
303
as a mask. By this, a bit contact hole BCH reaching one of the impurity regions of the selection transistor and a node contact hole NCH reaching the other of the impurity regions formed with diameters reduced to less than the limit of resolution of photolithography.
After forming the contact hole, a polycrystalline silicon film
305
is deposited to fill the contact holes BCH and NCH (FIG.
34
), then the polycrystalline silicon films
305
and
303
and the side wall
304
are etched back. This etchback is performed until the surface of the polycrystalline silicon film
305
and the side wall
304
become lower than the open faces of the preparatory contact holes. By this, as seen in
FIG. 35
, a plurality of poly-plugs
306
flared outward at the top are formed projecting from the impurity regions of the selection transistors STr.
In the step shown in
FIG. 36
, the BPSG film
205
is etched back to the same height as the surface of the poly-plug
306
. A silicon oxide film
207
is formed by the LP-CVD method using oxidation or thermal oxidation of TEOS by O
2
gas (hereinafter referred to as the “LP-TEOS method”), then a silicon nitride film
208
is formed over the entire surface by the LP-CVD method. This film is formed with a photoresist pattern R
12
for forming bit contact holes.
As shown in
FIG. 36
, the silicon nitride film
208
and the silicon oxide film
207
are etched using the formed photoresist pattern R
12
as a mask to expose the surface of the poly-plug
306
.
The photoresist pattern R
12
is removed, then a doped polycrystalline silicon layer
308
and a WSix layer
309
are deposited. A not illustrated photoresist pattern is formed for patterning the bit line, then this is used as a mask to etch the lower polyside film to form the bit line BL.
Next, the LP-TEOS method is used to form a thin silicon oxide film
210
and the LP-CVD method used to form by a thin silicon nitride film
211
thinly over the entire surface, then an NSG film
212
and BPSG film
213
are deposited by the O
3
-TEOS method and the BPSG film
213
is made to reflow to flatten its surface.
In the step shown in
FIG. 38
, the surface of the BPSG film
213
is lightly shaved by etching as needed in order to flatten it, then a silicon nitride film
214
acting as an etching stopper at the time of formation of the capacitor is deposited over the entire surface. A polycrystalline silicon film
310
is deposited thickly on this, then a photoresist pattern R
13
is formed for opening the position above the poly-plug
302
for node contact.
In the step shown in
FIG. 39
, first, the polycrystalline silicon film
310
is etched using the photoresist pattern R
13
as a mask to form a preparatory contact hole. Next, a further polycrystalline silicon film is deposited and etched back to form a side wall
31
made of polycrystalline silicon on the side face of the prepara
Coleman William David
Kananen, Esq. Ronald P.
Pham Long
Rader & Fishman & Grauer, PLLC
Sony Corporation
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