Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1999-04-16
2002-07-16
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
Reexamination Certificate
active
06420220
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method of fabricating a transistor.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g, transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate dielectric thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the FET, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. Additionally, reducing the size, or scale, of the components of a typical transistor also increases the density, and number, of the transistors that can be produced on a given amount of wafer real estate, lowering the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
However, the drive to increase the operating speed of the transistors is often hampered by the choice of materials that are typically used for the gate conductor, for example. One convenient and relatively inexpensive material for the gate conductor is polycrystalline silicon (polysilicon or poly). The polysilicon is typically doped, for example, with arsenic (As) for an N-channel metal oxide semiconductor FET (NMOSFET or NMOS transistor), or boron (B) for a P-channel MOSFET (PMOSFET or PMOS transistor), to render the polysilicon more conductive. The doping of the polysilicon may conveniently be accomplished by diffusing or implanting the dopant atoms or molecules through the upper surface of a polysilicon gate conductor. However, the dopant atoms or molecules may not penetrate all the way through the polysilicon gate conductor down to the gate dielectric, even when driven by a heat-treating process such as a rapid thermal anneal (RTA). This is often referred to as a “poly depletion effect,” and increases the resistivity and decreases the conductivity of the “poly depleted” polysilicon gate conductor, decreasing the operating speed of the transistor.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a method is provided for fabricating a semiconductor device, the method including forming a dielectric layer above a structure, forming a silicidable layer above the dielectric layer and forming a conductive layer above the silicidable layer. The method also includes forming a silicided layer by siliciding a portion of the conductive layer using at least a portion of the silicidable layer and forming a gate conductor having sides by patterning the silicided layer and the conductive layer.
In another aspect of the present invention, a semiconductor device is provided including a gate dielectric above a structure and a gate conductor above the gate dielectric. The gate conductor of the semiconductor device has sides and includes a silicided layer above the gate dielectric and a conductive layer above the silicided layer.
REFERENCES:
patent: 5424572 (1995-06-01), Solheim
patent: 5814537 (1998-09-01), Maa et al.
patent: 6140218 (2000-10-01), Liu et al.
Fulford H. Jim
Gardner Mark I.
May Charles E.
Advanced Micro Devices , Inc.
Elms Richard
Luu Pho
Williams Morgan & Amerson
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