Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Reexamination Certificate
1999-07-13
2002-07-23
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
C711S150000, C711S163000, C711S168000
Reexamination Certificate
active
06425043
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to memory systems for computers. More particularly, the present invention relates to the design of a memory interface that maintains a table indicating which banks of memory are currently in use so that during a memory access the system can rapidly determine if a bank conflict exists.
2. Related Art
As processor speed continually increase, memory systems are under increasing pressure to provide data at faster rates. This has recently led to the development of new memory system designs. Memory latencies have been dramatically decreased by using page mode and extended data out (EDO) memory designs, which achieve a high burst rate and low latencies within a single page of memory. Another recent innovation is to incorporate a synchronous clocked interface into a memory chip, thereby allowing data from within the same page of memory to be clocked out of the memory in a continuous stream. Such memory chips, with clocked interfaces are known as synchronous random access memories.
As memory latencies decrease, address decoding time is becoming a significant factor in limiting memory system performance. In many computer systems, memory is comprised of a plurality of banks, each one of which is able to service memory requests independently of other banks. Hence, it is possible to issue a memory request to a bank that is not busy while other banks are busy processing preceding memory requests. This bank-level parallelism can greatly improve system performance.
However, in memory systems with multiple banks extra memory decoding time is often required to determine if a bank conflicts exists. A bank conflict occurs when a memory access operation attempts to access a bank that is busy servicing a preceding memory request. Systems typically test for bank conflicts by comparing an address for a current request against all outstanding requests to determine if the current request is directed to a bank that is busy processing an outstanding memory request. If so, the system does not issue the current request to the bank until the bank becomes free.
Unfortunately, the additional decoding time required to check for bank conflicts can offset the performance gained by accessing memory banks in parallel. What is needed is a method and an apparatus that reduces the decoding time required to determine if a bank conflict exists.
SUMMARY
One embodiment of the present invention provides a method for rapidly determining whether a bank conflict exists during a memory access. The method operates by receiving an address as part of a memory access operation, and using the address to identify a target bank of memory to which the memory access operation is directed. The method next looks up an entry for the target bank of memory in a bank conflict table. This bank conflict table includes an entry for each bank of memory in the computer system. Each entry indicates whether a corresponding bank of memory is presently busy servicing a memory request. If the entry indicates that the target bank is not busy, the method immediately issues the memory access operation to the target bank of memory. Otherwise, the method stalls the memory access operation until the target bank becomes available.
In one embodiment of the present invention, the act of issuing the memory request includes setting an entry corresponding to the target bank of memory in the bank conflict table so that subsequent memory access operations will detect that the target bank of memory is busy. In a variation on this embodiment, the act of issuing the memory request further includes: issuing a RAS signal to the target bank of memory; issuing a CAS signal to the target bank of memory; and issuing a precharge signal to the target bank of memory. (Note that this precharge operation can also be accomplished by using a CAS signal with an autoclose command.) After issuing the RAS signal and the CAS signal, the method resets the entry for the target bank of memory in the bank conflict table so that subsequent memory access operations will detect that the target bank of memory is not busy.
In one embodiment of the present invention, the act of using the address to identify the target bank of memory takes place while the address is in transit through a core logic unit, and before the address arrives at a memory controller.
In one embodiment of the present invention, the bank conflict table is located in the memory controller.
REFERENCES:
patent: 5559970 (1996-09-01), Sharma
patent: 5875470 (1999-02-01), Dreibelbis et al.
patent: 6081873 (2000-06-01), Hetherington et al.
patent: 6298413 (2001-10-01), Christenson
Kim Matthew
Vital Pierre M.
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