Semiconductor device and method of fabricating the same

Details Semiconductor device and method of fabricating the same Semiconductor device and method of fabricating the same

1998-09-23

2002-07-09

Crane, Sara (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S754000

Reexamination Certificate

active

06417534

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, it relates to a semiconductor device which reduces a leakage current and improves its operating speed while electrically connecting an element of a memory cell region with that of a peripheral circuit region in an excellent state and a method of fabricating the same.
2. Description of the Prior Art
First, a method of fabricating a first exemplary conventional dynamic random access memory (hereinafter referred to as a DRAM), i.e., an exemplary conventional semiconductor device, is now described with reference to
FIGS. 54
to
78
.
Referring to
FIG. 54
, element isolation oxide films
2
a
and
2
b
are formed on prescribed regions of a silicon substrate
1
by trench isolation, for forming a memory cell region
1
a
and a peripheral circuit region
1
b.
Referring to
FIG. 55
, boron is injected into the memory cell region la and a first area of the peripheral circuit region
1
b
, for forming p-type wells
3
a
and
3
b
respectively.
Referring to
FIG. 56
, phosphorus is injected into a second area of the peripheral circuit region
1
b
, for forming an n-type well
4
.
Referring to
FIG. 57
, a gate oxide film
5
is formed on the silicon substrate
1
by thermal oxidation or the like. A polysilicon film and a tungsten silicide film
6
are formed on the gate oxide film
5
. A silicon oxide film
7
is formed on the tungsten silicide film
6
. Thereafter gate electrode portions
8
a
,
8
b
and
8
c
are formed by photolithography and etching.
Referring to
FIG. 58
, the n-type well
4
is covered with a photoresist pattern
48
a
and thereafter phosphorus is injected by ion implantation, for forming n
−
source/drain regions
9
a
,
9
b
,
9
c
and
9
d
. Thereafter the photoresist pattern
48
a
is removed.
Referring to
FIG. 59
, the p-type wells
3
a
and
3
b
are covered with a photoresist pattern
48
b
and thereafter boron is injected by ion implantation, for forming p
−
source/drain regions
10
a
and
10
b
. Thereafter the photoresist pattern
48
b
is removed.
Referring to
FIG. 60
, a silicon oxide film
11
is formed on the silicon substrate
1
, to cover the gate electrode portions
8
a
,
8
b
and
8
c.
Referring to
FIG. 61
, the silicon oxide film
11
is anisotropically etched for forming sidewall oxide films
12
on both side surfaces of the gate electrode portions
8
a
,
8
b
and
8
c
respectively.
Referring to
FIG. 62
, a photoresist film
48
c
is formed to cover the n-type well
4
. Thereafter the photoresist film
48
c
is employed as a mask for injecting phosphorus by ion implantation, thereby forming n
+
source/drain regions
13
a
,
13
b
,
13
c
and
13
d
. Thus formed is a MOS transistor T
1
of an LDD structure including n-type source/drain regions
15
a
and
15
b
and the gate electrode portion
8
a
. Further formed is a MOS transistor T
2
of an LDD structure including n-type source/drain regions
15
c
and
15
d
and the gate electrode portion
8
b
. Thereafter the photoresist film
48
c
is removed.
Referring to
FIG. 63
, a photoresist film
48
d
is formed to cover the p-type wells
3
a
and
3
b
. Thereafter the photoresist film
48
d
is employed as a mask for injecting boron by ion implantation, thereby forming p
+
source/drain regions
14
a
and
14
b
. Thus formed is a MOS transistor T
3
including p-type source/drain regions
16
a
and
16
b
and the gate electrode portion
8
c
. Thereafter the photoresist film
48
d
is removed.
Referring to
FIG. 64
, a silicon oxide film
17
is formed on the silicon substrate
1
to cover the gate electrode portions
8
a
,
8
b
and
8
c.
Referring to
FIG. 65
, a bit line contact hole
18
exposing a surface of the n-type source/drain region
15
b
is formed in the silicon oxide film
17
.
Referring to
FIG. 66
, a polysilicon film
40
is buried in the bit line contact hole
18
.
Referring to
FIG. 67
, a bit line
25
electrically connected to the polysilicon film
40
is formed on the silicon oxide film
17
.
Referring to
FIG. 68
, a silicon oxide film
26
is formed on the silicon oxide film
17
, to cover the bit line
25
.
Referring to
FIG. 69
, a storage node contact hole
41
a
exposing a surface of the n-type source/drain region
15
a
is formed in the silicon oxide films
17
and
26
.
Referring to
FIG. 70
, a polysilicon film
42
is buried in the storage node contact hole
41
a.
Referring to
FIG. 71
, a metal film of ruthenium or platinum is formed on the silicon oxide film
26
, and a storage node
28
a
is formed by prescribed photolithography and etching.
Referring to
FIG. 72
, a thin film of a high dielectric constant and a metal film of ruthenium or platinum are successively formed on the storage node
28
a
. Thereafter a capacitor dielectric film
28
b
and a cell plate
28
c
are formed by prescribed photolithography and etching. The storage node
28
a
, the capacitor dielectric film
28
b
and the cell plate
28
c
form a capacitor
28
.
Referring to
FIG. 73
, an interlayer insulation film
29
is formed on the silicon oxide film
26
, to cover the capacitor
28
.
Referring to
FIG. 74
, peripheral circuit contact holes
43
a
and
43
b
exposing surfaces of the n-type source/drain regions
15
d
and
15
c
are formed in the interlayer insulation film
29
and the silicon oxide films
17
and
26
. Further, peripheral contact holes
43
c
and
43
d
are formed to expose surfaces of the p-type source/drain regions
16
a
and
16
b
. At the same time, a cell plate contact hole
30
is formed to expose a surface of the cell plate
28
c
of the capacitor
28
.
Referring to
FIG. 75
, a titanium film
45
and a titanium nitride film
47
a
are formed in the cell plate contact hole
30
by sputtering or the like. Further, titanium films
22
c
,
22
d
,
22
e
and
22
f
and titanium nitride films
47
b
,
47
c
,
47
d
and
47
e
are formed in the peripheral circuit contact holes
43
a
,
43
b
,
43
c
and
43
d
respectively.
FIG. 76
shows a portion around the n-type source/drain region
15
d
and the p-type source/drain region
16
b
in this step in an enlarged manner.
Thereafter heat treatment is performed to react the titanium films
22
c
,
22
d
,
22
e
and
22
f
with silicon contained in the n-type source/drain regions
15
a
,
15
b
,
15
c
and
15
d
and the p-type source/drain regions
16
a
and
16
b
, for forming titanium silicide films
24
c
,
24
d
,
24
e
and
24
f
.
FIG. 77
shows the portion around the n-type source/drain region
15
d
and the p-type source/drain region
16
b
in this step.
Referring to
FIG. 78
, an aluminum copper film is formed on the interlayer insulation film
29
, and metal wires
33
are formed by prescribed photolithography and etching. Thereafter an interlayer insulation film (not shown) and a passivation film (not shown) are formed to cover the metal wires
33
, thereby completing the DRAM.
A method of fabricating a second exemplary conventional DRAM is now described with reference to
FIGS. 79
to
86
. After a step similar to that shown in
FIG. 63
described with reference to the first prior art, a silicon nitride film
56
is formed on a semiconductor substrate
1
to cover gate electrode portions
8
a
,
8
b
and
8
c
, as shown in FIG.
79
.
Referring to
FIG. 80
, a part of the silicon nitride film
56
formed on a peripheral circuit region
1
b
is removed. A silicon oxide film
17
is formed to cover the silicon nitride film
56
and the gate electrode portions
8
b
and
8
c
. A photoresist film
48
g
is formed on the silicon oxide film
17
. This photoresist film
48
g
is employed as a mask for anisotropically etching the silicon oxide film
17
, thereby forming an opening
62
exposing a surface of the silicon nitride film
56
.
Referring to
FIG. 81
, the photoresist film
48
g
is employed as a mask to anisotropically etch the silicon nitride film
56
, for forming a bit line contact hole
18
c
exposing a surf

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