Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1999-11-19
2002-09-17
Niebling, John F. (Department: 2811)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S149000
Reexamination Certificate
active
06451633
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to a semiconductor integrated circuit formed on an SOI substrate and, more particularly, to a semiconductor integrated circuit having a static electricity protection transistor formed on an SOI film over a substrate, and to a method for manufacturing the same.
2. Background Information
There is shown in
FIG. 7
a conventional static electricity protection transistor formed on a substrate having an SOI film. Meanwhile,
FIG. 8
shows a connection diagram thereof.
FIG. 7A
is a plan view as viewed from above
FIG. 7B
a sectional view taken on line (a—a) in a gate width direction, and
FIG. 7C
a sectional view taken on line (b—b) in a gate lengthwise direction. The conventional static electricity protection transistor is structured by a gate electrode
43
, a gate oxide film
40
, a channel region
57
, a source region
41
, a drain region
42
, a ground region
56
, an interconnect contact, metal interconnections
58
,
59
,
60
, and an interlayer insulation film
46
. As shown in the figure, the gate oxide film
40
is formed on the SOI film as a channel region. The gate electrode
43
is formed of polysilicon on the channel region
57
, on which the interlayer insulation film
46
is formed. Here, the static electricity protection transistor basically uses an N-type MOS transistor and hence the channel region SOI film is in a P-type. In some cases, a P-type transistor is employed. On an SOI wafer with a thin SOI film thickness, the source region
41
, drain region
42
and ground region
56
in depth direction reach the insulation film
2
on the substrate
1
. LOCOS
45
is formed in areas other than the channel region
57
, source region
41
, drain region
42
and ground region
56
. The LOCOS
45
reaches the insulation film
2
over the substrate
1
. Consequently, this LOCOS
45
completely separates the channel region
57
, source region
41
, drain region
42
and ground region
56
from the channel region, source region, drain region and ground region of another transistor.
As shown in
FIG. 8
, in the conventional static electricity protection transistor a pad
47
is connected to the drain region
42
of the static electricity protection transistor. The drain
42
is in turn connected to a semiconductor integrated circuit (semiconductor circuit). The source region of the static electricity protection transistor is connected to a ground terminal of the semiconductor integrated circuit. Here, for a static electricity protection transistor formed on an SOI film over a substrate through an insulation film, a gate electrode
43
is connected to a ground terminal through a resistance
48
. Also, if a static electricity protection transistor is formed on an SOI film in a same layout as that of a static electricity protection transistor formed on a bulk wafer, a gate electrode
43
will be in floating. The source region
41
is connected to the ground region
56
and ground terminal. Here, the ground region
56
formed on the SOI wafer is not electrically connected to the channel region
57
and substrate
1
, differently from a transistor formed on a bulk wafer. Consequently, the channel region
57
is floating in potential.
Furthermore, a method for manufacturing a conventional static electricity protection transistor is explained with reference to FIGS.
9
(A)-
9
(E),
10
(A)-
10
(E) and
11
(A)-
11
(C). An SOI film
19
is formed over a substrate
1
through an insulation film
2
(FIG.
9
A). An oxide film
50
is formed on the SOI film
19
(FIG.
9
B). Next, the oxide film
50
is patterned to form openings
51
for alignment marks (FIG.
9
C). This is placed in a thermal oxidation furnace to form a thermal oxide film
52
(FIG.
9
D). At this time, the SOI film silicon positioned at the openings
51
of the oxide film
50
is oxidized greater than the SOI film silicon having the oxide film
50
. Consequently, a thermal oxide film
52
at the opening
51
is greater in thickness than other portions. If the thermal oxide film
52
is removed, recess steps are formed as shown in
FIG. 9E
which are alignment marks
53
. Then, an oxide film
54
and nitride film
55
for LOCOS are formed and patterned (FIG.
10
A). After patterning the nitride film
55
, LOCOS
45
is formed in an oxide furnace as shown in FIG.
10
B.
Next, the nitride film
55
and the oxide film
54
in areas other than the LOCOS
45
are removed, and thereafter a gate oxide film
40
is formed (FIG.
10
C). Furthermore, the polysilicon film is formed and patterned to form a gate electrode
43
(FIG.
10
D). Then, as shown in
FIG. 10E
, N-type ions are implanted to the source/drain region
41
,
42
. Further, as shown in
FIG. 11A
, P-type ions are implanted to a ground region
56
. Next, as shown in
FIG. 11B
an interlayer insulation film
46
is formed. Thereafter, contact holes are formed and then the interlayer insulation film
46
is planarized by a reflow process, followed by forming metal interconnections
58
,
59
,
60
as shown in
FIG. 11C. A
static electricity protection transistor thus formed is connected as shown in FIG.
8
.
In the conventional static electricity protection transistor constructed as above, when static electricity enters the pad, surface breakdown occurs between the drain and the substrate to flow charges toward the substrate being in a ground level. The flowing charges to the substrate raises a potential on the substrate to thereby induce bipolar operation between the drain region, the channel region and the source region. Thus, current flows through a path of the drain, the substrate and the source.
In the static electricity protection transistor formed on a bulk wafer, a substrate contact is provided around the static electricity protection transistor, thereby bringing a substrate potential to a ground level. However, a transistor is formed on an SOI wafer having a small semiconductor film thickness on an insulation film thereof by the conventional CMOS forming method, and the SOI film in a depth direction will be entirely formed as a source/drain region. Consequently, even if a substrate contact is provided around the transistor as in the conventional transistor, the potential of the channel region (or substrate potential) is in a floating condition. Due to this, the charge flowing to the channel region of the static electricity protection transistor due to surface breakdown has nowhere to exit, resulting in an abrupt increase in the channel region potential. Bipolar operation, if induced herein, is satisfactory. However, if a large amount of chargers [more in amount] enter the channel region, there arises a problem that electrostatic breakdown or Joule thermal breakdown possibly occurs because that region is very small in size and hence low in capacitance for accepting charges.
Meanwhile, where bipolar operation occurs through the drain region, channel region and source region, the static electricity protection transistor formed on a bulk wafer has a source connected to a substrate ground region so that the charges entered the source region can be released toward the substrate. However, in the static electricity protection transistor formed on an SOI wafer having an small SOI film thickness on an insulation film, a source region is directly connected to a ground terminal of a semiconductor integrated circuit. Accordingly, the charges entered the source region have nowhere to escape so that there is a possibility that they flow to other transistors connected to the ground line and induce electrostatic breakdown.
Furthermore, where bipolar operation occurs through the drain region, channel region and source region to flow large current through the transistor, large heat generation occurs on the transistor. In the conventional transistor formed on a bulk transistor, because the transistor at its lower side is connected with a substrate, heat dissipates through the substrate. On the SOI wafer, however, the transistor at its lower side is covered by an oxide film tha
Adams & Wilks
Niebling John F.
Seiko Instruments Inc.
Whitmore Stacy
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