Electrical computers and digital processing systems: processing – Processing control – Branching
Reexamination Certificate
1999-07-20
2002-09-17
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: processing
Processing control
Branching
C712S214000, C712S021000
Reexamination Certificate
active
06453412
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to digital computers, and particularly to digital computers capable of executing instructions in parallel.
Traditional computers which receive a sequence of instructions and execute the sequence one instruction at a time are known. The instructions executed by these computers operate on single-valued objects and hence are referred to as “scalar” machines. The operational speed of traditional scalar computers has been pushed to its limits by advances in circuit technology and computer architecture. However, with each new generation of machines, new mechanisms for accelerating must be devised for traditional scalar machines.
A common approach is instruction pipelining. A pipelined processor decodes traditional macro- or assembly-level instructions into a sequence of micro-instructions. The micro-instructions are distributed across a series of sequentially organized execution stages: fetch, translate/decode, register access, address calculation, data modify, and data write. Pipeline execution enables more than one macro-instruction to be processed at a time.
Another approach for accelerating the computational speed of single-processor devices is found in the RISC (reduced instruction set computer) architecture that employs a limited set of very simple instructions. An approach taken along more traditional lines is the CISC (complex instruction set computer) architecture which is based upon a minimal set of complex multi-operand instructions. Adapting an existing scalar computer architecture would require a fundamental alteration of its underlying structure. More significantly, the consequent change to its instruction set would require substantial re-investment by software vendors to in order to produce code that could run on such a machine.
In an effort to apply to scalar machines some of the benefits realized with RISC machines, so-called “superscalar” computers have been developed. These machines are essentially scalar machines whose performance is increased by adapting them to execute more than one instruction at a time from an instruction stream including a sequence of single scalar instructions. These machines typically decide at instruction execution time whether two or more instructions in a sequence of scalar instructions may be executed in parallel. The decision is based upon the operation codes (OP codes) of the instructions and on data dependencies which may exist between instructions. An OP code signifies the computational hardware required for an instruction. In general, it is not possible to concurrently execute two or more instructions which utilize the same hardware (a hardware dependency) or the same operand (a data dependency). These hardware and data dependencies prevent the parallel execution of some instruction combinations. In these cases, the affected instructions must be executed serially.
The foregoing detection and recovery schemes require complex hardware to track the progress of each instruction, and determine which, if either of the instructions, creates an exception. The tracking mechanisms usually send down, along with each instruction, the address for that instruction, in addition to other state or control information necessary to pick up execution of the instruction at the time of the exception. The hardware associated with tracking each instruction in a pipeline, for multiple instruction paths, is costly and complex. This disadvantage becomes even more pronounced as the complexity of the instruction set increases.
There is a need for a mechanism which provides parallel execution paths and at the same time facilitates exception handling. It is desirable to provide a detection and recovery scheme that does not require the use of complex hardware, thus easing the design effort and minimizing the system cost in terms of needed silicon and power consumption.
SUMMARY OF THE INVENTION
One aspect of the present invention provides, in a computer having a single execution pipeline, a method for executing paired MMX-type instructions. The method includes executing two MMX-type instructions as paired MMX instructions; if execution of the paired MMX instructions causes an exception, disabling paired execution, and re-executing the two MMX-type instructions in sequential fashion; and enabling paired execution following the re-executing.
Another aspect of the present invention comprehends, in a computing device, a method for executing instructions. The method includes fetching a first instruction; prior to execution of the first instruction, fetching a second instruction; determining whether the first and second instructions are both MMX-type instructions and, if the first and second instructions are not both MMX-type instructions, then sequentially executing the first and second instructions; if the first and second instructions are both MMX-type instructions, determining whether both MMX-type instructions can be executed in parallel; if both MMX-type instructions can be executed in parallel, then feeding both MMX-type instructions to an execution unit, whereby both MMX-type instructions are executed in parallel; if an exception occurs during parallel execution of both MMX-type instructions, disabling parallel execution and executing both MMX-type instructions sequentially; and re-enabling parallel execution following sequential execution of a second one of both MMX-type instructions.
A further aspect of the present invention contemplates a computing device. The computing device has an MMX execution and a translation unit. The MMX execution unit receives micro-instructions for execution. The MMX execution unit can execute two micro-instructions in parallel. The translation unit is coupled to the MMX execution unit. The translation unit determines whether a sequential pair of MMX-type instructions can be executed in parallel, and issues a first micro-instruction and a second micro-instruction to the MMX execution unit for parallel execution, where, upon occurrence of an exception during paired execution, the translation unit re-issues the first and second micro-instructions to the MMX execution unit for sequential execution, and where, upon completion of sequential execution, the translation unit allows subsequent pairs of the MMX-type instructions to be paired for parallel execution.
Yet another aspect of the present invention comprehends a processor that has an MMX execution unit, exception handling logic, and a translation unit. The MMX execution unit receives micro-instructions for execution. The MMX execution unit can execute two micro-instructions in parallel, and is configured to detect a paired exception that occurs during parallel execution of the two micro-instructions. The exception handling logic is coupled to the MMX execution unit. The exception handling logic handles exceptions that occur during execution of sequentially executed micro instructions, and indicates an occurrence of the paired exception. The translation unit is coupled to the exception handling logic. The translation unit receives indication of the occurrence, and disables parallel execution, and issues a first of the two micro-instructions followed by a second of the two micro-instructions for sequential execution, and re-enables parallel execution following issue of the second of the two-micro-instructions.
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Henry G. Glenn
Parks Terry
Huffman James W.
Huffman Richard K.
IP First L.L.C.
Lee Thomas
Trujillo James K.
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