Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Decoding
Reexamination Certificate
2000-11-20
2002-03-26
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Decoding
C326S106000, C326S108000, C365S230060
Reexamination Certificate
active
06362658
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of electronic circuits, and, more particularly, to memory devices. More specifically, the invention relates to a decoder for memories having an optimized configuration. That is, the invention relates to a decoder, particularly for column decoding in memories, which has substantially no voltage-dependent functionality limitation, which may be produced with minimal area consumption, and is suitable for use in small spaces.
BACKGROUND OF THE INVENTION
One layout for driving the selection lines of a multiplexer in a conventional prior art non-volatile memory is shown in FIG.
1
. This circuit layout is simple, compact, and widely used in the field of non-volatile memories. These memories are generally developed for applications using operating voltages in the range of 4.5 to 5.5 volts. Thus, the compatibility of the performance and of the functionality of the layout shown in
FIG. 1
is generally sufficient for such operating voltages.
Even so, non-volatile memories which operate at low voltages (i.e., 2.7-3.3 volts and even 1.6-2.0 volts) are increasingly required. In this context, the layout shown in
FIG. 1
, being close to the operating limit, is affected by slowing (“meta-stability”) in its operation. This slowing negatively affects the performance of the entire memory.
Multiplexers in general are designed to select the lines of the memory to be pre-charged. Any slowing thereof leads to an increase in the time required to reach the operating levels and therefore ultimately leads to a longer read time. This is true even in the presence of suitable boost circuits.
Yet, the need to improve the performance of decoders clearly cannot disregard the stringent need to provide a circuit network with a minimal number of devices. That is, the space available for placement of the decoding structure is typically limited in conventional architectures of non-volatile memories.
Two further prior art implementations with a wider operating voltage range are schematically shown in
FIGS. 2 and 3
. A prior art circuit with fourteen transistors (four more than an embodiment using the conventional approach), in addition to the buffer, is shown in
FIG. 2. A
more compact prior art circuit which uses only ten transistors (again in addition to the buffer), matching the number of devices of the conventional structure, is shown in FIG.
3
.
The examples of
FIGS. 1
,
2
and
3
include decoders with four inputs and sixteen lines. The circuit structure shown in
FIG. 3
, however, is not compact enough to meet the area saving requirements that occur in the manufacture of non-volatile memories.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a decoder for memories having an optimized configuration, where the number of devices (transistors) used is further reduced with respect to prior art circuits to allow placement in the most advantageous position of the memory.
Another object of the present invention is to provide a decoder for memories having an optimized configuration whose operation is substantially compatible with circuit portions supplied with different supply voltages and is substantially independent from the supply voltage.
Still another object of the present invention is to provide a decoder for memories having an optimized configuration in which there is a predominance of N-channel devices, which are notoriously faster and more compact than P-channel devices.
Yet another object of the present invention is to provide a decoder for memories having an optimized configuration in which there are no decoupling structures, consequently simplifying decoding management.
A further object of the present invention is to provide a decoder for memories having an optimized configuration with minimization of inversions before producing the final switching of the selected line starting from the main address lines.
An additional object of the present invention is to provide a decoder for memories which has a high performance even at the lowest operating voltages that may be used for the operation of the memories.
One other object of the present invention is to provide a memory decoder which has a highly flexible structure that can perform a selection of a “1” line in a “0” field and vice-versa, substantially without altering the circuit structure.
Furthermore, still another object of the present invention is to provide a memory decoder that is highly reliable and relatively simple to manufacture at competitive costs.
These and other objects, which will become more apparent hereinafter, are provided by a decoder with reduced complexity including at least one OR circuit section and at least one AND circuit section. The at least one OR section may include first and second circuit lines that are mutually connected and respectively receive an address signal and an inverted address signal. Furthermore, the AND section may include first and second circuit lines which respectively receive the inverted address signal and the address signal. The OR circuit section and the AND circuit section may be respectively connected to first and second booster circuits. Also, the at least one OR circuit section may include a virtual ground.
REFERENCES:
patent: 5773995 (1998-06-01), Crocker
patent: 6064234 (2000-05-01), Masuda et al.
patent: 6087855 (2000-07-01), Frederick, Jr. et al.
patent: 6144227 (2000-11-01), Sato
patent: 6222788 (2001-04-01), Forbes et al.
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
STMicroelectronics S.r.L.
Tan Vibol
Tokar Michael
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