Static information storage and retrieval – Read/write circuit
Reexamination Certificate
1998-12-29
2002-01-15
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
C365S149000, C365S131000
Reexamination Certificate
active
06339550
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
MOS dynamic random access memory arrays are susceptible to occasional single bit soft errors caused by random alpha particle radiation. This invention relates to an improved dynamic random access memory architecture that is completely immune to single bit soft errors.
2. Description of the Prior Art
Each single bit memory cell in a MOS dynamic random access memory (DRAM) is very simple, consisting of one transistor connected to one capacitor, where the amount of charge on the capacitor determines whether a ‘one’ or a ‘zero’ is stored in the cell. This memory cell is susceptible to having the charge on its capacitor destroyed if a random energetic alpha particle strikes the capacitor or a junction of its connecting transistor. When subsequently data is read from the cell it will be incorrect, causing a “soft error.” The larger the DRAM memory the more likely it is to have one or more soft errors during any given period of time.
FIG. 1
shows a small portion of the core of a DRAM chip, where a capacitor Cb and a transistor Tb comprise the cell for one memory bit, and the diode Db represents the inherent junction between the source and body of Tb. Data for this bit is stored as a charge on the capacitor Cb; if logic 1 represents a charge on Cb then logic 0 will represent no charge. The access transistor Tb places charge from the bit line BL onto Cb during writing and extracts charge from Cb onto BL during reading. The word line WL turns Tb on or off at the appropriate times.
When Tb places a charge from Cb onto BL, the voltage change of BL will be smaller than a full logic swing, because the stray capacitance of the bit line BL is significantly larger than the capacitance Cb. However, it is possible to design a sense amplifier to detect this small voltage change if the amplifier is made differential, by adding another reference bit line input BLR. As shown in
FIG. 1
, BLR is connected to a reference capacitor Cr through a reference transistor Tr, whose gate is driven by the reference word line WLR. Cr is made equal to Cb, and before Cr is connected to BLR it is charged to a reference voltage Vr by transistor Tp
3
, where Vr is less than the logic 1 voltage written onto Cb, but greater than 0. For example, if Cb is initially charged to Vp, when writing a logic 1, and since junction leakage will over time reduce the voltage on Cb, it would be appropriate to set Vr~Vp/4. So that later, when transistors Tb and Tr are turned on at the same time, there will be a positive or a negative differential signal on the bit line pair BL and BLR, depending on whether the voltage remaining on Cb is higher or lower than Vp/4 respectively. After detecting the polarity of this signal the sense amplifier will charge Cb either to a full voltage of Vp or to 0.
A bit in a DRAM chip can either be read from or written to. In either case, first a whole row of memory cells connected to a word line WL is read, then refreshed. Next after refreshing, and if in a read cycle, the data from a selected bit on the row of cells is transferred to an output on the chip, or if in a write cycle, the data from this selected bit is overwritten by new data from an input on the chip.
There are three phases in a DRAM memory cycle, Precharge, Sense, and Refresh/Read/Write:
During Precharge &phgr;p goes high enabling bit lines BL and BLR to be charged to the same potential Vp through transistors Tp
1
and Tp
2
, and the capacitor Cr to be charged to a reference voltage Vr through transistor Tp
3
.
During Sense the word lines WL and WLR simultaneously go high turning on transistors Tb and Tr which connect capacitors Cb and Cr to BL and BLR respectively. The sense amplifier determines whether the charge on Cb is more or less than the reference charge on Cr, by determining the differential voltage between BL and BLR.
During Refresh/Read/Write, while WL and WLR are still high, if the sense amplifier had sensed the voltage on BL (V
BL
) to be larger than the voltage on BLR (V
BLR
) it will write a full charge back into Cb, and if it had sensed V
BL
to be smaller than V
BLR
it will write 0 charge back into Cb. If this is a read cycle the output of the sense amplifier will be sent to chip a output, and if this is a write cycle the sense amplifier will write new data into Cb from a chip input.
The capacitance Cb can be either a dielectric capacitor or a PN junction capacitor. If Cb is a PN junction then it will be reverse biased when charge is stored on it. This reverse bias will cause a depletion region across the junction. An energetic alpha particle striking the depletion region will cause a momentary short across the depletion region, which will drain the charge from Cb resulting in a soft error. If Cb is a dielectric capacitor, it will be impervious to alpha particles. However, there still is an inherent junction from the source of transistor Tb to ground represented by the diode Db. This junction will be reverse biased with a depletion region when a charge is stored on Cb. This Db depletion region can be momentarily shorted by an alpha particle, resulting in charge loss of Cb, and a soft error.
SUMMARY OF THE INVENTION
A single bit soft error in a DRAM chip is almost always a result of charge being lost on the storage capacitor of the memory cell, where this charge loss is caused by an ionizing particle passing through the junction associated with the capacitor. Therefore, if logic 1 represents charge on this capacitor and logic 0 represents no charge, then a single bit soft error occurs when a stored bit changes from logic 1 to logic 0, and not when a bit changes from logic 0 to logic 1.
The present invention corrects for soft errors automatically in a DRAM chip by storing redundantly a single bit in two memory cells, because it is highly unlikely that two cells will simultaneously have soft errors caused by charge loss in their storage capacitors. This invention describes circuitry to output a logic 1 if during cell readout either or both cells are storing a logic 1, and to output a logic 0 only if both cells are storing a logic 0.
In this invention every time a bit is read or refreshed any potential soft errors are corrected, by writing correct data into both memory cells associated with each bit. This invention has a negligible speed penalty for DRAM access time.
REFERENCES:
patent: 5969996 (1999-10-01), Muranaka et al.
patent: 6151242 (2000-11-01), Takashima
Le Vu A.
Nguyen Van-Thu
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