Method and system for controlling the memory access...

Details Method and system for controlling the memory access... Method and system for controlling the memory access...

1999-06-18

2002-09-03

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S167000

Reexamination Certificate

active

06446172

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial No. 88103131, filed Mar. 2, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to computer memory access operation, and more particularly, to a method and system used in a computer system to control the memory access operation by a central processing unit (CPU) in a more efficient manner by reducing the period of wait states for L
1
write-back signals.
2. Description of Related Art
In this information age, computers have become an indispensable office tool, in all walks of life. In the use of computers, performance is a primary concern. Many factors can affect the performance of a computer system, including the speed of the CPU, the type of the primary memory being used, efficiency of memory access control, and so forth. Presently, dynamic random-access memory (DRAM) is widely used as the primary memory of most computer systems. Conventional memory access methods that can help boost the computer performance include, for example, the Fast Page Mode (FPM) method and the Extended Data Out (EDO) method. Moreover, a new type of DRAM, called synchronized DRAM (SDRAM), allows fast access speed to the data stored therein.
FIG. 1
is a schematic block diagram of a conventional memory access control method and system, as indicated by the reference numeral
120
, which is designed for controlling the memory access operation by a CPU, as indicated by the reference numeral
110
, on a memory unit, as indicated by the reference numeral
130
.
The memory access control system
120
is coupled between the CPU
110
and the memory unit
130
and is composed of a CPU interface
121
and a memory control unit
122
. The CPU
110
further includes a cache memory
112
. The CPU
110
and the CPU interface
121
are interconnected via a number of data lines ADS, REQ, HITM, HTRDY, DBSY, DRDY, and HD, all of which are described later in detail; the CPU interface
121
and the memory control unit
122
are interconnected via two data lines DADS and DAT; and the memory control unit
122
and the memory unit
130
are interconnected via two data lines CMD and MD.
The access operation by the CPU
110
to the memory unit
130
, whether read or write, is controlled by the memory access control system
120
. The data communication between the CPU
110
and the memory control unit
122
is controlled by the CPU interface
121
. When the CPU
110
wants to gain access to the memory unit
130
, it issues and transfers access requests via the CPU interface
121
to the memory control unit
122
. In write operations, the memory control unit
122
is used to control the writing of the output data from the CPU
110
into the memory unit
130
; and whereas in read operations, the memory control unit
122
controls the retrieval of the CPU-requested data from the memory unit
130
and then transfers the retrieved data via the CPU interface
121
to the CPU
110
.
When the CPU
110
wants to gain access to the memory unit
130
, it first sets the ADS data line at a LOW-voltage logic state. The intended access operation of either write or read is indicated by the logic voltage state of the REQ data line. Moreover, whether the request is a hit or a miss to the cache memory
112
at updated data is indicated by the logic voltage state of the HITM data line. For instance, in the case of a cache hit, the HITM data line is set at a LOW-voltage logic state, and whereas in the case of a cache miss, the HITM data line is set at a HIGH-voltage logic state. The HTDRY signal is accordingly used by the CPU to export the data to be written back. When the DRDY and DBSY data lines are set at a LOW-voltage logic state, this indicates that the CPU interface
121
wants to transfer data via the HD data line to the CPU
110
.
Furthermore, the CPU interface
121
and the memory control unit
122
use the DADS and DAT data lines for data communication therebetween. The DADS signal is a converted version of the ADS signal from the CPU
110
. The DAT data line is used to transfer the output data from the CPU
110
that are to be written into the memory unit
130
, or the data that are retrieved from the memory unit
130
and to be transferred via the CPU interface
121
to the CPU
110
.
The memory control unit
122
and the memory unit
130
use the CMD and MD data lines for data communication therebetween. The CMD data line is used to transfer access control signals to the memory unit
130
, while the MD data line is used to transfer data to and from the memory unit
130
.
To read data from the memory unit
130
, the CPU
110
successively issues a number of read requests. If any one of the read requests is a hit to the cache memory
112
, the CPU
110
uses the HITM data line to issue an L
1
write-back signal to indicate such a condition to the memory control unit
122
, and in which case, a cache write-back operation is performed to write the cache data back into the memory unit
130
. Typically, the L
1
write-back signal of each read request is issued several clock cycles after the read request is issued. The conventional memory access control system
120
operates in such a manner that, for each read request from the CPU
110
, the CPU interface
121
sends out a corresponding internal read-request signal to the memory control unit
122
until the L
1
write-back signal of the current read request is received. In response to this internal read-request signal, the memory control unit
122
then performs a read operation to retrieve the requested data from the memory unit
130
and then transfers the retrieved data via the CPU interface
121
to the CPU
110
.
Therefore, there exists a wait state in which the conventional system waits until the L
1
write-back signal of the current read request is issued by the CPU
110
for the CPU interface
121
to issue the internal read-request signal to the memory control unit
122
. Typically, the overall memory access operation performed by a CPU includes 60% read operation, 15% cache write-back, and 25% write operation. Therefore, the overall system performance of a computer system can be enhanced by solely increasing the speed of the read operation. The conventional method and system of
FIG. 1
, however, is low in read operation since it must frequently wait for L
1
write-back signals.
SUMMARY OF THE INVENTION
It is therefore an objective of the invention to provide a method and system for controlling the memory access operation performed by a CPU, which can help increase the speed of the read operation performed by the CPU so that the overall system performance of the computer system can be enhanced.
In accordance with the foregoing and other objectives of the invention, a new method and system is proposed for use in a computer system to control the memory access operation performed by a CPU on a memory unit in a more efficient manner.
The memory access control method and system of the invention is characterized by the prompt issuance of the internal read-request signal for each read request from the CPU to the memory control unit, promptly after it is issued and without waiting until the L
1
write-back signal of the read request is issued. If one read request is later found to be a hit to the cache memory, a read-stop signal is promptly issued to stop the current read operation on the memory unit, and then a cache write-back operation is performed to write the cache data back to the memory unit.
The method of the invention includes the following steps: (1) in response to the current read request from the CPU, promptly issuing an internal read-request signal to the memory unit without waiting until the CPU issues the L
1
write-back signal of the current read request; (2) in response to the internal read-request signal, performing a read operation on the memory unit; and (3) if the current read request is a hit to the cache memory, generating a read-stop signal to stop the curre

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