Static information storage and retrieval – Powering
Reexamination Certificate
2000-08-17
2002-03-12
Elms, Richard (Department: 2824)
Static information storage and retrieval
Powering
C327S536000, C327S540000
Reexamination Certificate
active
06356499
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a power supply circuit and a semiconductor memory device having such a power supply circuit, and more particularly to a single-source type power supply circuit including a booster circuit and a non-volatile semiconductor memory device having such a power supply circuit.
FIG. 1
is a schematic circuit diagram of a typical booster circuit to be used for a power supply circuit.
The booster circuit includes diodes D
1
through D
6
, capacitors C
1
through C
5
and capacitor Ca, and inverters G
1
, G
2
.
The anode of the diode D
1
is supplied with external supply voltage Vcc. The cathodes of the diodes D
1
through D
5
are respectively connected to the anodes of the diodes D
2
through D
6
and the anodes of the diodes D
2
through D
6
are also connected to the first terminals of the capacitors C
1
through C
5
respectively. The other ends of the capacitors C
1
, C
3
and C
5
are connected to the-output terminal of inverter G
1
whose input terminal is fed with clock signal OSC generated by an oscillator. The input terminal of the inverter G
1
operates as the signal input terminal of the booster circuit. The other ends of the capacitors C
2
and C
4
are fed with clock signal OSC. The cathode of the diode D
6
outputs voltage Vccint. A stabilizing capacitor Ca is connected between the cathode of the diode D
6
and ground.
Electric charges are transferred from diode to diode in an alternating manner in the booster circuit in accordance with clock signal OSC fed from an oscillator. As a result, it generates voltage Vccint that is higher than external supply voltage Vcc.
FIG. 2
is a schematic circuit diagram of a typical oscillator to be used for a power supply circuit.
The first input terminal of NAND-gate
1
is fed with signal CPE for enabling the booster circuit. The output terminal of the NAND-gate
1
is connected to, for example, a 4-stage inverter
2
including four serially connected inverters. The output signal of the 4-stage inverter
2
is fed to the second input terminal of the NAND-gate
1
. For example, an inverted signal of the output signal of the inverter
2
is used as clock signal OSC.
When signal CPE rises to a high level, the oscillator outputs a clock signal OSC that alternately rises to a high level and falls to a low level. When signal CPE goes to a low level, the oscillator stops oscillating and outputs a low level signal.
FIG. 3
is a circuit diagram of a known power supply circuit including a booster circuit as shown in FIG.
1
and an oscillator as shown in FIG.
2
. The power supply circuit provides a booster circuit system typically used for a non-volatile semiconductor memory device.
The oscillator
12
and the booster circuit
13
have respective circuit configurations identical with those illustrated in
FIGS. 2 and 1
. The output voltage Vccint of the booster circuit
13
is divided by resistor
17
and supplied to the inverted input terminal of a differential amplifier
11
. The non-inverted input terminal of the differential amplifier
11
is supplied with reference voltage Vref. The differential amplifier
11
supplies signal CPE to the oscillator
12
.
The differential amplifier
11
compares the reference Voltage Vref and the voltage obtained by regulating the voltage Vccint and turns on/off the booster circuit
13
in accordance with the outcome of the comparison. In this way, the output voltage (boosted voltage) Vccint of the booster circuit
13
is held to a desired level that may be, for example, equal to 10V.
As shown in
FIG. 3
, the output voltage Vccint of the booster circuit
13
is supplied to regulator circuit
14
and Y-selector
16
.
For example, the regulator circuit
14
may generate a voltage of 6.5V in the write (program) verify mode of operation, and a voltage of 10V which is equal to the output voltage Vccint in the write (program) mode. Likewise, it may generate a voltage of 2.5V in the erase mode, and a voltage of 3.5V in the erase verify mode.
The output voltage Vout of the regulator circuit
14
is supplied to row decoder
15
. The row decoder
15
selects a word line of a memory cell array (not shown) in accordance with a row select signal.
The Y-selector
16
selects a bit line of the memory cell array (not shown) in accordance with a column select signal.
The output voltage Vccint of the booster circuit
13
is subjected to a variety of loads.
Firstly, the capacitance of the Y-selector
16
itself provides a load.
Additionally, in the write (program) mode, the regulator circuit
14
directly applies the obtained voltage Vccint to the row decoder
15
. Accordingly, the capacitance
18
of the word line (which is selected by the row decoder
15
and to which the output voltage Vccint of the booster circuit
13
is directly supplied) makes a load for the voltage output terminal of the booster circuit
13
. On the other hand, in the erase mode, the write verify mode or the erase verify mode, the output voltage Vccint of the booster circuit
13
is shifted to a lower voltage by the regulator circuit
14
and, therefore, the capacitance
18
of the word line does not make any load. Therefore, the load to be added to the voltage Vccint varies depending on the mode of operation.
FIGS. 4A and 4B
show operating waveforms of the power supply circuit, or waveforms of the output voltage Vccint that may appear when the booster circuit
13
of the power supply circuit in
FIG. 3
starts operating and the output voltage Vccint rises from 0V to 10V.
FIG. 4A
shows a waveform of the output voltage Vccint that may be observed when there is a heavy load typically in the write (program) mode, whereas
FIG. 4B
shows a waveform of the output voltage Vccint that may appear when there is only a light load typically in the erase mode.
In the case of a light load as shown in
FIG. 4B
, the voltage Vccint overshoots to show a zig-zag waveform because of the light load and makes it difficult to output a well controlled stable voltage Vccint. When an overshot voltage Vccint is supplied from the power supply circuit to a device the circuit drives, it may exceed the withstand voltage level of the device and hence can degrade the performance of the device and damage its reliability.
In view of these problems, therefore, it is highly desirable to reduce the fluctuations in the output voltage of a power supply circuit that appear when a light load is applied to the voltage output terminal of the booster circuit and make it possible to provide a well controlled voltage from the booster circuit. Thus, there is a strong demand for a power supply circuit that can improve the reliability of any device it drives and also for a semiconductor memory device having such a power supply circuit.
Meanwhile, known non-volatile semiconductor memory devices include flash EEPROMs. A flash EEPROM includes stacked transistors having a floating gate and a control gate as memory cells. Such a memory cell changes its threshold voltage for data writing/erasing operations as electrons are charged into and discharged from it through the floating gate.
Flash memories adapted to be charged with hot electrons for data writing are currently driven either by a two-source type power supply circuit that uses a power supply of Vcc=5V for data writing and another power supply of Vpp=12V for data erasing, or by a single-source type power supply circuit that uses only a power supply of Vcc=5V. When a single-source type power supply circuit is used, power supply voltage Vpp for data erasing is obtained by means of a booster circuit.
The trend in recent years is in favor of power saving low voltage power supply circuits and 3V is typically used as power supply voltage. From the viewpoint of convenience, a single-source type power supply circuit may be superior to a two-source type power supply circuit.
Now, when the power supply voltage of a known power supply circuit adapted to supply the voltage directly to the control gate in the read mode is reduced from 5V to 3V, then the voltage supplied to the
Atsumi Shigeru
Banba Hironori
Banner & Witcoff , Ltd.
Elms Richard
Nguyen Van Thu
LandOfFree
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