Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-06-12
2002-05-21
Sherry, Michael J. (Department: 2829)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
Reexamination Certificate
active
06391763
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for forming a plug or damascene trench. In particular, it relates to a method for forming a plug or damascene trench on a semiconductor device with a wet etch process.
BACKGROUND OF THE INVENTION
In the semiconductor manufacturing industry, the etch process plays an important role in the fabricating process of a semiconductor device. The etch process is to remove a portion of the deposited thin film according to the pattern transferred from a photomask by chemical reactions or physical actions. Therefore, the desired semiconductor device will be successfully fabricated. At the present time, there are two etch techniques employed in the semiconductor fabricating process: one is wet etch, which etches the deposited thin film by chemical reactions; and the other is dry etch, which etches the deposited thin film by physical actions.
Comparing the wet etch process with the plasma reactive ion etch (plasma RIE) process, which is a dry etch process combining the properties of the sputtering etch process and the plasma etch process, the wet etch process has the following advantages:
1. The underlayer of the semiconductor device will be damaged if plasma RIE is employed, whereas employing the wet etch process will not damage the underlayer of the semiconductor device.
2. The selectivity of the wet etch process is significantly higher than that of the plasma RIE process.
3. The top comer rounding effect will automatically emerged if the wet etch process is employed so that the subsequent metal filing process can be carried out more easily.
Unfortunately, because the wet etch process is an isotropic etch process, the critical dimension (CD) will be difficult to control when the wet etch process is employed to form a via/contact or is employed to damascene trench technique. That will severely affect the progress of the subsequent fabrication processes and lower the yield of the semiconductor devices fabricated thereby.
There arises a need to develop a method for forming a plug or damascene trench on a semiconductor device with a wet etch process such that the metal filling process can be carried out more easily, and the plug or damascene trench formed thereby has a better CD control ability.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a method for forming a plug or damascene trench on a semiconductor device with a wet etch process such that the plug or damascene trench has a better CD control ability.
The method for forming a semiconductor structure on a semiconductor device according to the present invention includes the following steps: depositing a dielectric layer on the semiconductor device, depositing a mask layer on the dielectric layer, removing a portion of the mask layer and defining the remaining portion of the mask layer as a hard mask, processing the portion of the dielectric layer not covered with the hard mask, removing the portion of the dielectric layer covered with the hard mask with a wet etch process, in which the wet etch rate of the portion of the dielectric layer not covered with the hark mask is significantly lower than that of the portion of the dielectric layer covered with the hard mask to create an opening in the dielectric layer, and filling the opening in the dielectric layer with a conducting material.
In accordance with the present invention, the dielectric layer is a spin-on-glass (SOG) material, and more preferably, a hydrogen silsesquioxane (HSQ) with a thickness of about 2000 to 20000 Å.
In accordance with the present invention, wherein before the mask layer is deposited, the dielectric layer is further processed by a thermal cure process at an ambient temperature of about 300-500° C.
Certainly, the mask layer is made of a hard mask material with a thickness of about 10-1000 nm.
Alternatively, the hard mask material is one selected from a group consisting of polysilicon, oxide, silicon nitride, silicon-oxy-nitride, titanium nitride, titanium-oxy-nitride, aluminum oxide, or silicon carbide.
In accordance with the present invention, the step of removing a portion of the mask layer and defining the remaining portion of the mask layer as a hard mask further includes the steps of: forming a patterned photoresist layer onto a portion of the mask layer, removing a portion of the mask layer according to the pattern on the patterned photoresist layer, and removing the photoresist layer.
In accordance with the present invention, the step of removing a portion of the mask layer according to the pattern on the patterned photoresist layer is executed by a plasma etch process.
In accordance with the present invention, the step of processing the portion of the dielectric layer not covered with the hard mask is executed by an electron-beam cure process.
Preferably, the electron-beam cure process is processed with a substrate temperature of about 300-500° C., a dosage of about 1000-10000 &mgr; c/cm
2
, and an energy of about 1-20 Kev.
In accordance with the present invention, the hard mask is removed by a chemical mechanical polishing (CMP) process or a plasma reactive ion etch (plasma RIE) process.
Preferably, the etching agent of the wet etch process is a diluted hydrofluoric acid (HF) solution or a buffered hydrofluoric acid (BHF)solution.
Noticeably, the wet etch rate of the portion of the dielectric layer being cured by electron-beam is significantly lower than that of the portion of the dielectric layer not being cured by electron-beam.
Preferably, the conducting material is a kind of metal material or a ploysilicon.
In accordance with the present invention, the semiconductor structure formed thereby is a plug or damascene trench.
Now the foregoing and other features and advantages of the present invention will be more clearly understood through the following descriptions with reference to the accompanying drawings, in which:
REFERENCES:
patent: 6165695 (2000-12-01), Yang et al.
Alston & Bird LLP
Kilday Lisa
Sherry Michael J.
Winbond Electronics Corp.
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