Semiconductor device with DMOS and bi-polar transistors

Details Semiconductor device with DMOS and bi-polar transistors Semiconductor device with DMOS and bi-polar transistors

1999-02-26

2002-03-19

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S370000, C257S339000, C257S341000, C257S342000, C257S413000

Reexamination Certificate

active

06359318

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device mounting a DMOS (Double diffusion Metal Oxide Semiconductor) transistor and a bipolar transistor in a mixed manner, and a method of manufacturing the same.
2. Description of the Background Art
A semiconductor device having a DMOS transistor and a bipolar transistor mounted in a mixed way has been disclosed in Japanese Patent Laying-Open No. 8-321556, for example. Hereinafter, a technique disclosed in the document will be described as an example of a conventional semiconductor device and a manufacturing method thereof, particularly focusing on a high voltage DMOS transistor and an npn bipolar transistor.
FIGS. 14A and 14B
are cross sectional views schematically showing a configuration of a conventional semiconductor device.
Referring to
FIGS. 14A and 14B
, regions RA and RB are regions for forming a high voltage DMOS transistor and a low voltage DMOS transistor, respectively. A region RC is a CMOS (Complementary Metal Oxide Semiconductor) transistor forming region. Regions RD and RE are npn type and pnp type bipolar transistors forming regions, respectively, and a region RF is an EEPROM (Electrically Erasable Programmable Read Only Memory) cell forming region.
In high voltage DMOS transistor region RA, a high voltage n type well region
144
is formed on a p type substrate
141
, with an n
+
region
142
interposed therebetween.
On the surface of high voltage n type well region
144
, a p type region
101
consisting of a relatively deeply formed p type body region
101
b
and a relatively shallowly formed p type channel region
101
a
is formed. In p type region
101
, an n type source region
102
is formed. A gate electrode layer
106
is formed opposite to p type region
101
that is sandwiched between high voltage n type well region
144
and n type source region
102
, with a gate insulating layer
105
interposed therebetween. Gate electrode layer
106
has an end portion extending to overlay a field oxide film
151
, and has side surfaces each covered with a respective sidewall insulating layer
107
.
In npn bipolar transistor region RD, a high voltage n type well region
144
and an n
+
buried region
114
are formed on p type substrate
141
, with an n
+
region
142
interposed therebetween. On the surface of high voltage n type well region
144
, a p type base region
111
consisting of a relatively shallowly formed p type region
111
a
and a relatively deeply formed p type body region
111
b
is formed. An n
+
emitter region
112
is formed in p type base region
111
. An n
+
collector contact region
114
is formed on the surface of n
+
buried region
114
.
Note that high voltage DMOS transistor region RA and npn bipolar transistor region RD, for example, are electrically isolated from other element forming regions by p type isolating regions
143
, p type well regions
145
a
, upper region isolating regions
145
b
, and field oxide films
151
.
Next, a method of manufacturing p type region
101
of the high voltage DMOS transistor and base region
111
of the npn bipolar transistor in this semiconductor device will be described.
FIGS. 15A
,
15
B,
16
A and
16
B are simplified cross sectional views showing, in the order of process steps, a method of manufacturing the conventional semiconductor device. Referring first to
FIGS. 15A and 15B
, a photoresist
161
is patterned by normal photolithography, and using the resist pattern
161
as a mask, a polycrystalline silicon (polysilicon) layer
171
is subjected to etching, to selectively expose the substrate surface. A p type dopant, e.g., boron, is ion implanted into thus exposed regions at 150 to 250 keV, substantially at a right angle with respect to the substrate surface. Accordingly, a p type body region
101
b
is formed in high voltage DMOS transistor region RA, and a p type body region
111
b
is formed in npn bipolar transistor region RD. Thereafter, resist pattern
161
is completely removed.
Referring to
FIGS. 16A and 16B
, a p type dopant, e.g., boron, is again implanted into the regions exposed from polysilicon layer
161
at about 150 keV, at an angle of about 30° to 45° with respect to the perpendicular of the substrate surface. Accordingly, a p type channel region
101
a
is formed in high voltage DMOS transistor region RA, and a p type region
111
a
is formed in npn bipolar transistor region RD. Thus, p type channel region
101
a
and p type body region
101
b
constitute a p type region
101
in high voltage DMOS transistor region RA, and p type region
111
a
and p type body region
111
b
constitute a p type base region
111
in npn bipolar transistor region RD.
Thereafter, a gate electrode layer is formed by patterning polysilicon layer
171
, a sidewall insulating layer
107
is formed to cover sidewalls of the gate electrode layer, and n type source region
102
, n
+
emitter region
112
and others are formed. The semiconductor device as shown in
FIGS. 14A and 14B
is thus completed.
The above-described conventional semiconductor device and the manufacturing method thereof, however, suffer from problems that the threshold voltage Vth of the DMOS transistor is hard to control freely, and that a rapidly operating npn bipolar transistor is difficult to realize. These will now be described in detail.
In the conventional manufacturing method, as shown in
FIGS. 16A and 16B
, an impurity is ion implanted using as a mask polysilicon layer
171
that is to be a gate electrode, to form p type channel region
101
a
in high voltage DMOS transistor region RA. Since heat treatment causes this p type channel region
101
a
to diffuse, its end portion SB at the substrate surface extends to directly beneath the gate electrode layer
106
, as shown in FIG.
17
.
An overlapping length L
0
of p type channel region
101
a
and p type body region
101
b
in the channel region posed between n type source region
102
and high voltage n type well region
144
thus becomes long. Accordingly, it is almost impossible to control the threshold voltage Vth of high voltage DMOS transistor independently and solely by p type channel region
101
a
. The longer the overlapping length L
0
, the more difficult to control the threshold voltage Vth.
As an approach to realize a rapidly operating bipolar transistor, there is a technique to narrow the width (so-called base width) W of base region
111
directly beneath n
+
emitter region
112
, as shown in FIG.
18
. To decrease base width W, it is necessary to make p type region
111
b
of high concentration so as to increase a breakdown voltage of base region
111
. When making p type region
111
b
of high concentration, however, p type body region
101
b
shown in
FIG. 17
, that is to be formed at the same time as p type region
111
b
, also becomes of high concentration. Such high concentration p type body region
101
b
leads to longer diffusion length of the impurity within p type body region
101
b
, and hence, longer overlapping length L
0
of p type channel region
101
a
and p type body region
101
b
. Therefore, it becomes still more difficult to control the threshold voltage Vth of the DMOS transistor.
In other words, in order to allow easy control of the threshold voltage Vth of DMOS transistor, base width W of the npn bipolar transistor should be made sufficiently large. This, however, makes difficult to realize an npn bipolar transistor that can operate at high speed.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device which permits easy control of the threshold voltage Vth of DMOS transistor and facilitates realization of a rapidly operating bipolar transistor, and a manufacturing method thereof.
The semiconductor device according to the present invention is specifically a semiconductor device having an insulated gate type field effect transistor, which includes: a semicondu

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