Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2001-05-10
2002-05-14
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S189020, C365S189120
Reexamination Certificate
active
06388928
ABSTRACT:
FIELD OF INVENTION
The invention pertains to the field of manufacturing of analog integrated chips. In particular to methods of adjusting fabricated circuits to compensate for unavoidable differences inherent in the semiconductor manufacturing process.
BACKGROUND
The manufacturing of an integrated circuit (chip) is an inexact process. Uncontrolled variations in manufacturing result in each chip having a unique set of electrical parameters. The types, sizes and distributions of these differences are well known. These variances are contrary to the goal of the manufacturing process, which is the production of quantities of identical devices. Since the variances cannot be eliminated, it ultimately falls upon designers to devise a mechanism to address this variability.
Digital design techniques are generally quite tolerant of a wide range of device characteristics, resulting in devices with differences in speed. System-level design techniques, such as synchronous clocking, allow for the use of a device with a wide range of characteristics, if it is above a specified minimum speed.
Analog designers have a more difficult problem; minute variations in device characteristics can result in large changes in the overall response. Often, the digital designer's techniques of overcoming these variances are inappropriate for the analog designer. The techniques used by analog designers can be roughly divided into two categories. In the first category, circuit techniques automatically compensate for inter-device variance. Unfortunately, for many design problems, an automatic compensation circuit is not known or is prohibited. In the second category, each individual device is characterized and adjusted to provide compensation for parametric variation.
A common technique for adjusting individual devices is to augment a circuit with an element, such as a digital to analog converter, whose output provides influence on the response sufficient to compensate for inter-device variations. We will refer to this type of circuit element as a compensator. Each circuit is tested to determine the correct setting of the compensator for that circuit. Since it is the desire of the analog circuit vendor to provide quantities of chips that appear identical, the individual setting for the compensator is preferentially stored within the device itself using a non-volatile digital memory. This programming is done by the vendor before delivery of the chip to the customer. Thus, the customer sees the desired end—quantities of identical chips. Any of the well-known non-volatile digital memory techniques can be used to store the individual setting including: programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), FLASH memory and others; however, EEPROM is frequently used, as it is simpler to construct within a typical analog semiconductor fabrication process.
The testing of the circuit is done by programming the non-volatile memory to each of its possible values in turn and then measuring the response of the circuit on the chip. From these measurements, the optimal setting of the compensator is determined and programmed into the memory for final shipment. In some cases, the response characteristics of the analog circuit may allow testing less than every possible setting of the non-volatile memory. For example, if the analog circuit response is monotonic with respect to compensator settings, then on average only one half of the possible settings need be measuring before observing the optimal value.
The increasing capability of the semiconductor manufacturing process (due to the shrinking of minimum critical dimensions) has lead to two key trends in the analog-chip market. One trend is an increase in the number and complexity of circuits integrated onto a single chip. Another trend is an increase in the precision of these circuits. These two trends have combined to increase the number of programmable bits, for the setting of compensators, present on an analog chip.
Correspondingly, each individual chip must spend greater amounts of time in the test process as each of the possible compensator values is tried and measured. The programming of non-volatile memory is known to be a slow process, causing it to consume the largest part of the test time. Often, the amount of time spent in the testing process is a significant, if not a dominant, portion of the manufacturing cost of the chip. Accordingly, a method of reducing the time spent testing a chip to determine the setting of its compensators is needed.
SUMMARY OF THE INVENTION
The standard compensator circuit is augmented with an additional digital register and multiplexer, removing the need to program the non-volatile memory for each possible compensator setting. The time to test each possible compensator setting is correspondingly reduced, resulting in a dramatic reduction in test time for the entire device.
REFERENCES:
patent: 5870621 (1999-02-01), Walsh et al.
patent: 5933594 (1999-08-01), La Joie et al.
Myers Theodore M.
Orlando Richard V.
Fernandez & Associates LLP.
Summit Microelectronics Inc.
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