Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2000-04-11
2002-05-28
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000, C365S230030, C365S230060, C365S225700
Reexamination Certificate
active
06396748
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device having regular word lines, spare words lines, and an address storage unit for storing replacement information of the regular word lines and spare word lines, and more particularly to a method and apparatus for setting word addresses as redundancy data in the address storage unit.
2. Description of the Prior Art
Currently, semiconductor memory devices such as RAMs (Random Access Memories) are utilized in various types of electronic equipment, and such a semiconductor memory device has an increasingly larger capacity and higher integration. However, several problems exist in manufacturing semiconductor memory devices of a large capacity and high integration with high yields. For this reason, currently, a redundant configuration is generally employed in which spare memory cells are provided in a semiconductor memory device at the manufacturing, and such a spare memory cell replaces a memory cell having a defect found in an inspection. Various approaches exist for arranging spare memory cells, and for example, spare memory cells are provided based on word lines.
A typical semiconductor memory device includes a number of memory cells arranged in two-dimensional array, each memory cell connecting to one of a plurality of bit lines and one of a plurality of word lines. Some semiconductor memory devices divide such a number of memory cells into a plurality of operation blocks in the arranging direction of the word lines such that one of word lines is activated in the respective operation blocks simultaneously. In such a semiconductor memory device, the number of actually arranged word lines may be reduced to a fraction of the data length of a bit address, and stored data of a plurality of bits may be read in parallel at a time. When spare word lines are provided as described above in such a semiconductor memory device which simultaneously activates word lines in a plurality of operation blocks, a number of regular word lines and a few spare word lines are generally arranged in each operation block. A regular word line refer to a word line to be used in normal times, i.e. when no defect is present.
The internal configuration of a conventional semiconductor memory device of such a structure will be now described with reference to FIG.
1
. Description is made for a DRAM (Dynamic RAM) used as a semiconductor memory device.
DRAM
1000
comprises a number of memory cells
1001
which are two-dimensionally arranged in a row direction and a column direction to constitute a memory cell array. In DRAM
1000
, the memory cell array is divided into a plurality of operation blocks “a”, “b”, . . . in the column direction. A number of regular word lines
1002
and a few spare word lines
1003
in parallel with the row direction are arranged along the column direction. Similarly, a plurality of bit lines
1004
in parallel with the column direction are arranged in the row direction. A plurality of memory cells
1001
belonging to the same row share one word line and are connected thereto. A plurality of memory cells
1001
belonging to the same column are connected to one bit line
1004
.
Each memory cell
1001
has a unique cell address set therefor, each of word lines
1002
,
1003
has a unique word address set therefor, and each bit line
1004
has a unique bit address set therefor.
Memory cells
1001
connected to regular word lines
1002
are provided for use in normal times, i.e. when no defect is present. On the other hand, memory cells
1001
connected to spare word lines
1003
are provided as an alternative when a defect is present. Since the memory cell array comprising a number of memory cells
1001
is divided into a plurality of operation blocks “a”, “b”, along the column direction as described above, each of the plurality of operation blocks “a”, “b”, . . . is provided with a plurality of regular word lines
1002
and one spare word line
1003
in DRAM
1000
. Respective word lines
1002
,
1003
are individually connected to word drivers
1005
for driving word lines. Similarly, respective bit lines
1004
are individually connected to sense amplifiers
1006
for driving bit lines. Sense amplifiers
1006
are integrated for each operation block to constitute sense amplifier array SA.
Sense amplifiers
1006
and word drives
1005
are connected to one address decoder
1007
which converts a cell address into word addresses and a bit address. However, word control circuit
1008
for controlling the replacement of a regular word line with a spare word line is interposed in the connection between address decoder
1007
and word drivers
1005
.
Address decoder
1007
receives a cell address as an external input and generates a plurality of word addresses and one bit address from the provided cell address. The word addresses generated cause corresponding word drives
1005
to be simultaneously activated, resulting in a plurality of regular word lines
1002
being activated simultaneously. Sense amplifier
1006
activates one bit line
1004
corresponding to the generated bit address. Specifically, sense amplifier array SA decodes the bit address to activate a bit line corresponding to the bit address.
It should be noted that DRAM
1000
herein illustrated is previously set such that a plurality of word addresses generated from a cell address activate one regular word line
1002
in respective operation blocks of a predetermined combination of (“a” and “c”) and (“b” and “d”).
Word control circuit
1008
includes fuse ROM
1009
for storing addresses. Fuse ROM
1009
has previously set data which indicates regular word lines
1002
to be replaced and replacing spare word lines
1003
. Word control circuit
1008
compares a word address generated by address decoder
1007
with word addresses of regular word lines to be replaced set in fuse ROM
1009
, and if a match occurs, causes word driver
1005
to activate spare word line
1003
at a replacing word address. If the word address generated by address decoder
1007
does not match any of word addresses of regular word lines to be replaced, the replacement of the word line is not performed, and a regular word line at the word address generated by address decoder
1007
is activated.
A case where a regular word line is not replaced with a spare word line is now considered.
When DRAM
1000
is provided with a cell address from the outside, address decoder
1007
generates a plurality of word addresses and a bit address, and a plurality of regular word lines
1002
and bit line
1004
are activated corresponding to the address data. This causes a memory access such as data writing and data reading to be performed to a memory cell located at an intersection point of activated regular word lines
1002
and activated bit line
1004
corresponding to the cell address. At this point, one word line
1002
is activated in each of two operation blocks of a predetermined combination as described above, which is substantially equivalent to a structure with two operation blocks connected in a vertical direction, thereby making it possible to access to one memory cell
1001
in a double range of the data length of the bit address. In this manner, conventional DRAM
1000
simultaneously activates one bit line
1004
and one regular word line
1002
in respective operation blocks of a predetermined combination to perform a memory access to one memory cell
1001
. However, the memory access become invalid when a defect is present in memory cell
1001
or regular word lines
1002
to be activated.
For this reason, in manufacturing DRAM
1000
as described above, memory cells
1001
and regular word lines
1002
are inspected at the final step. If a defect is found, the word address of regular word line
1002
having the found defect is set as a target to be replaced in fuse ROM
1009
, and only DRAMs
1000
for which this data setting is completed are shipped as products.
In DRAM
1000
with data setting completed, a word address generated from
McGinn & Gibb PLLC
NEC Corporation
Tran Andrew Q.
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