Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2000-11-07
2002-09-24
Gossage, Glenn (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S169000, C365S185330
Reexamination Certificate
active
06457092
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor storage device employing flash memories. More particularly, it relates to a technique for continuously writing data into a semiconductor disk pack or the like which employs flash memories.
2. Description of the Related Art
A flash EEPROM (electrically erasable programmable read-only memory) is adapted to read out data therefrom and write data thereinto in word units with one word consisting of a plurality of bits, and to electrically erase data therefrom in chip units or in plural-word units. With respect to known art, there is a storage device, e.g., a disk pack wherein a plurality of such flash EEPROM's are packaged, and wherein data are written into the flash EEPROM's or erased therefrom in succession.
The prior art will be explained in conjunction with FIGS.
8
(
a
)-
8
(
g
) which are illustrative of timing waveforms for the operation of writing data into a flash memory in accordance with a known command control system. Symbol Vcc in the figure denotes the power supply voltage of the flash memory, and +5V is normally applied as this voltage Vcc. Symbol Vpp denotes a writing supply voltage, which is a potential higher than the power supply voltage Vcc and which is applied in the mode of writing data into the flash memory. Addresses serve to designate the data writing areas of the flash memory in byte units. An output enable signal OE is set at a “low” level in the mode of reading data out of the flash memory, whereas it is set at a “high” level in any other mode. A chip enable signal CE is set at a “low” level in the mode of reading a command and data out of or writing a command and data into the flash memory. The chip enable signal CE in this flash memory is used also as a write enable signal, and the data are written at the rising or leading edge of this signal CE under the conditions of the high potential of the writing supply voltage Vpp and the high level of the output enable signal OE. Symbol I/
07
and symbols I/
100
-I/
106
indicate signals on data lines. Next, the operation of writing 1 byte of data into the flash memory will be explained. First, the command on each data line is written into the flash memory at the rising edge of the chip enable signal CE. The command is a write setup command which notifies the start of the 1-word data writing operation to the flash memory. After the command has been written, the data on each data line is written into the flash memory at the rising edge of the chip enable signal CE. The “low” duration of the chip enable signal CE in the case of writing the command and the data is 50 nanosec. or more. In actuality, however, the operation of writing the data into a memory chip has just begun within the flash memory, and the next data cannot be written until the end of the internal writing operation. Here, a time period of several microsec.—several tens microsec. is expended on the internal writing operation within the flash memory, and it is considerably long compared with the time period, i.e., the actual time used, for writing the command and the data of one word. In this regard, status polling can be utilized as an expedient for checking if the writing operation within the flash memory chip has ended after the lapse of the time period of several microsec. about several tens microsec. The status polling determines the end of the writing operation within the memory chip in such a way that the status of the data line I/
07
is read out by holding the signals CE and OE “low”.
The above technique requires a considerable time period in the case of continuously writing the data of a plurality of words. The command and the data of one word can be written in a time period on the order of several tens nanosec . . . about several hundred nanosec. However, a time period of several microsec.—several tens microsec. is expended from the time data of one word is initially fed to the flash memory until the end of the writing operation within the flash memory chip, and the flash memory cannot be accessed in the meantime. Therefore, the total time period for writing data of one word is considerably longer than a time period for reading out data of one word. Moreover, in the case of continuously writing data of the plurality of words, the writing time period increases in proportion to the number of words. By way of example, in a case where a semiconductor disk pack is constructed using such flash memories, data of several kilowords about several tens kilowords or more are continuously written. Then, the writing time period increases in proportion to the quantity of the data to-be-written, so that the transfer of the data which are to be written becomes slow, and this affects the whole system.
SUMMARY OF THE INVENTION
It is accordingly an object of the present invention to provide a semiconductor storage device which shortens a time period for writing data.
In order to accomplish this object, in one aspect of the present invention, a semiconductor storage device comprises a plurality of flash memories which store data therein; and control means for sending a first instruction of writing the data to one of the flash memories, and for sending a second write instruction to another of the flash memories different from the flash memory to which the first write instruction has been sent and which is under a write operation, before the flash memory to which the first instruction has been sent becomes capable of accepting a next write instruction.
Each of the flash memories is slower in the data writing operation than in a data reading operation. Nevertheless, since the control means sends the write instructions to the different flash memories in succession, a large amount of continuous data can be written at high speed when the storage device is considered overall.
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Yoshi Tokushige et al., “Future vision of Nand ty
Kaki Kenichi
Katayama Kunihiro
Tsunehiro Takashi
Antonelli Terry Stout & Kraus LLP
Gossage Glenn
Hitachi , Ltd.
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