Method and apparatus to prevent latch-up in CMOS devices

Details Method and apparatus to prevent latch-up in CMOS devices Method and apparatus to prevent latch-up in CMOS devices

1997-09-19

2002-03-19

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S206000, C257S372000, C257S373000

Reexamination Certificate

active

06359316

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a CMOS device, methods of making and using these devices, and method of preventing latch-up.
2. Discussion of the Art
CMOS devices have a variety of advantages, such as improved switching speed and power dissipation. However, these devices can suffer from latch-up.
Latch-up is a well understood and documented phenomenon which results from parasitic bipolar transistors present in the CMOS device. When a CMOS device experiences latch-up, there is a large self-sustaining current flow between power supply terminals which can lead to destruction of the device, and can only be stopped by disconnecting the power supply. Latch-up is a local phenomenon, and methods for preventing latch-up typically adjust the location or architecture of the CMOS device. CMOS devices, the latch-up phenomenon, as well as a variety of methods for preventing latch-up, are described in U.S. Pat. Nos. 4,647,956; 4,660,067; 5,055,903; 5,159,204; 5,379,147; and 5,406,513; as well as in
Device Electronics for Integrated Circuits
, 2
nd
Edition, Richard S. Muller and Theodore I. Kamins, pp. 454-467 (John Wiley & Sons, 1986).
FIG. 1
illustrates a CMOS device
2
including elements to prevent latch-up. The substrate
8
is a P-type substrate. A set of P-channel transistors
46
are in an N-well
4
while a set of N-channel transistors
48
are in the P-type substrate
8
. The set of P-channel transistors
46
have P+ diffusion regions
6
and
7
which may act as sources and drains. Similarly, the set of N-channel transistors
48
have N+ diffusion regions
16
and
17
which may act as sources or drains. Both sets of P-channels transistors
46
and N-channel transistors
48
have gates
10
. As illustrated, there are a plurality of contacts
18
and
19
which electrically connect a P+ diffusion region
7
or N+ diffusion region
17
to either Vcc 12 or Vss 14, respectively, via buses
20
or
22
, respectively. In order to inhibit latch-up, additional contacts
24
and/or
26
are placed on the periphery of the device, and are electrically connected to Vcc
12
or Vss
14
, via buses
20
or
22
, respectively. The primary differences between diffusion regions
7
and
17
include (a) the bus electrically coupled to
7
and
17
and (b) the dopant conductivity type (P vs. N).
FIG. 2
illustrates another way of preventing latch-up. Only a set of N-channel transistors
48
of the CMOS device
2
are shown in this figure. Similarly to
FIG. 1
, the set of N-channel transistors
48
include N+ diffusion regions
16
and
17
and gates
10
. Also present are contacts
19
which electrically connect N+ diffusion region
17
to Vss
14
via bus
22
. In order to prevent latch-up in this device, a “tap” P+ diffusion
28
is electrically connected to Vss
14
via contact
30
and bus
22
.
FIG. 3
illustrates yet another way of preventing latch-up. Similarly to
FIG. 1
, CMOS device
2
has a set of P-channel transistors
46
and a set of N-channel transistors
48
. The set of N-channel transistors include N+ diffusion regions
16
and
17
, gates
10
, and contacts
19
electrically connecting diffusion region
17
to Vss
14
via bus
22
. The set of P-channel transistors
46
include P+ diffusion regions
6
and
7
, gates
10
, and contacts
18
electrically connecting diffusion region
7
to Vcc
12
via bus
20
, all located within N-well
4
. To prevent latch-up, the P-channel transistors are surrounded by guard ring
32
which functions to collect the excess majority carriers in the N-well, and thereby isolate the circuit element from excess carriers which may exist outside the guard ring. The guard ring is a “tap” N+ diffusion. Similarly, the N-channel transistors are surrounded by guard ring
34
composed of a “tap” P+ diffusion.
A major disadvantage of the above-described methods for preventing latch-up is that they all require a significant increase in the die size of the CMOS device. Accordingly, there is a great need for a way to prevent latch-up which does not increase the size of the CMOS device.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a CMOS device with resistance to latch-up, but which does not have an enlarged die size.
Another object of the invention is to provide a CMOS device having a high ratio of latch-up voltage to power supply voltage.
Another object of the invention is to provide a method of making such CMOS devices.
Another object of the invention is to provide methods for using such CMOS devices.
Another object of the invention is to provide a method of inhibiting latch-up without increasing die size.
These objects are made possible by a semiconductor device, comprising (i) a set of at least one P-channel transistors, (ii) a set of at least one N-channel transistors, (iii) a latch-up inhibitor P+ tap region, and (iv) a latch-up inhibitor N+ tap region, wherein the sets of P-channel and N-channel transistors are complementary.


REFERENCES:
patent: 4288804 (1981-09-01), Kikuchi et al.
patent: 4651190 (1987-03-01), Suzuki et al.
patent: 4937645 (1990-06-01), Ootsuka et al.
Webster's II New Riverside University Dictionary, 1984.

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