Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2001-03-23
2002-09-17
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S156000
Reexamination Certificate
active
06452432
ABSTRACT:
RELATED APPLICATION
This application claims the benefit of Korean Patent Application No. 2000-16883, filed Mar. 31, 2000, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates generally to signal processing circuits and, more particularly, to delay locked loop (DLL) circuits and methods of operating same.
BACKGROUND OF THE INVENTION
A delay locked loop (DLL) circuit may be used in an integrated circuit device to generate an internal clock signal based on an external clock signal that is provided to the integrated circuit device. Various circuits in the integrated circuit device may then use the internal clock signal. The DLL circuit may have a duty-cycle corrector circuit that is electrically connected thereto and adjusts the duty-cycle of the external clock signal to approximately 50%. The DLL circuit may derive the internal clock signal from the duty-cycle corrected clock signal.
FIG. 1
is a block diagram of a conventional DLL circuit and a duty-cycle corrector circuit. Referring now to
FIG. 1
, the duty-cycle corrector circuit
111
is connected in series with the DLL circuit
121
. The duty-cycle corrector
111
corrects the duty-cycle of the external clock signal Clk_ext and generates a duty-cycle corrected clock signal Clk_dcc at an output terminal thereof. The DLL circuit
121
receives the duty-cycle corrected clock signal Clk_dcc and generates an internal clock signal Clk_int at an output terminal thereof. Unfortunately, both the duty-cycle corrector circuit
111
and the DLL circuit
121
may introduce jitter into the internal clock signal Clk_int. As shown in
FIG. 2
, the duty-cycle corrector circuit
111
may introduce jitter in the duty-cycle corrected clock signal Clk_dcc as represented by tl. Moreover, the DLL circuit
121
may introduce additional jitter into the internal clock signal Clk_int. The combined jitter in the internal clock signal Clk_int, which is introduced by the duty-cycle corrector circuit
111
and the DLL circuit
121
, is represented by t
2
.
Conventional integrated circuit devices may include a duty-cycle corrector circuit that is electrically connected in series to the input of a DLL circuit and/or a duty-cycle corrector circuit that is electrically connected in series to the output of a DLL circuit
121
. The additional duty-cycle corrector circuit may increase the jitter in the internal clock signal Clk_int. The jitter contained in the internal clock signal Clk_int may cause circuits in the integrated circuit device that use the internal clock signal Clk_int to malfunction. Accordingly, there exists a need for improved signal processing circuits that can generate clock signals having reduced jitter.
SUMMARY OF THE INVENTION
According to embodiments of the present invention, a signal processing circuit comprises a first delay locked loop (DLL) circuit that generates a first intermediate output signal in response to an input signal and a phase difference between a leading edge of a reference signal and a leading edge of a feedback signal and a second DLL circuit that generates a second intermediate output signal in response to the input signal and a phase difference between a trailing edge of the reference signal and a trailing edge of the feedback signal. Because the first and second intermediate output signals are based on the phase difference between the reference signal and the leading and trailing edges of a feedback signal, respectively, and the first and second intermediate output signals are not derived from the reference signal, the jitter that may be introduced into the first and second intermediate output signals may be reduced.
A mixer circuit may be used to generate an output signal in response to the first and second intermediate output signals. In particular embodiments, the mixer circuit generates a leading edge transition of the output signal in response to a leading edge transition of the first intermediate output signal and the mixer circuit generates a trailing edge transition of the output signal in response to a trailing edge transition of the second intermediate output signal. In accordance with embodiments of the present invention, the output signal and the feedback signal may be the same signal or a delay circuit may be used to generate the feedback signal in response to the output signal.
A duty-cycle corrector circuit may generate the reference signal in response to the input signal. Although the reference signal may have a duty-cycle of approximately 50%, the reference signal may contain jitter caused by the duty-cycle corrector circuit. The first and second intermediate output signals are based on the phase difference between the leading and trailing edges, respectively, of the reference signal and the feedback signal. Advantageously, because the jitter component in the reference signal typically has a higher frequency than the loop bandwidth of the first and second DLL circuits, the first and second intermediate output signals may be unaffected by jitter in the reference signal. Accordingly, jitter in the output signal may be reduced.
The mixer circuit may comprise a flip-flop circuit that generates the output signal in response to a set signal and a reset signal, which are generated by first and second logic circuits in response to the first and second intermediate output signals, respectively.
The first and second DLL circuits may comprise a delay unit that generates a plurality of delay signals corresponding to delayed versions of the input signal. The first DLL circuit may further comprise a first phase comparator circuit that determines the phase difference between the leading edge of the reference signal and the leading edge of the feedback signal and a first multiplexer that generates the first intermediate output signal by selecting a first one of the plurality of delay signals in response to the phase difference between the leading edge of the reference signal and the leading edge of the feedback signal. In particular embodiments, a first register may be used to latch the phase difference between the leading edge of the reference signal and the leading edge of the feedback signal so as to provide the phase difference to the first multiplexer.
The second DLL circuit may further comprise first and second inverters that generate a complementary reference signal and a complementary feedback signal, respectively, a second phase comparator circuit that determines the phase difference between the trailing edge of the reference signal and the trailing edge of the feedback signal, and a second multiplexer that generates the second intermediate output signal by selecting a second one of the plurality of delay signals in response to the phase difference between the trailing edge of the reference signal and the trailing edge of the feedback signal. In particular embodiments, a second register may be used to latch the phase difference between the trailing edge of the reference signal and the trailing edge of the feedback signal so as to provide the phase difference to the second multiplexer.
In further embodiments of the present invention, the first and second DLL circuits discussed above may be used to generate clock signals in integrated circuit memory devices. For example, because the first and second intermediate output signals may have reduced jitter, an input receiver circuit may generate processed data in response to input data and the first and second intermediate output signals. A memory cell array may store the processed data therein in response to the first and second intermediate output signals. In particular embodiments, interface logic may be used to couple the processed data from the input receiver circuit to the memory cell array, and an output buffer may be used to generate output data in response to the data stored in the memory cell array and the first and second intermediate output signals.
Thus, in summary, embodiments of the present invention may be used to generate a duty-cycle corrected signal from an original signal with
Le Dinh T.
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
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