Synchronous semiconductor memory device capable of reducing...

Details Synchronous semiconductor memory device capable of reducing... Synchronous semiconductor memory device capable of reducing...

1999-06-16

2002-07-16

Ray, Gopal C. (Department: 2181)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S733000, C365S201000

Reexamination Certificate

active

06421789

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device and a method of testing the same, and more specifically, it relates to an input/output circuit inputting/outputting data in synchronization with a clock, a synchronous semiconductor memory device including the same and a method of testing the same.
2. Description of the Prior Art
In general, a data input/output circuit employed for a semiconductor device such as a semiconductor memory device, for example, puts a plurality of outputted data out of phase with an internal clock thereby transferring the data from the semiconductor memory device to an external device at a rate higher than the clock frequency.
In order to reduce a test cost, a BIST (built-in self test) structure providing a function of performing read and write tests of memory cells on a chip itself is increasingly employed.
FIG. 67
is a block diagram showing the block structure of a conventional memory having a BIST (built-in self test) function.
Referring to
FIG. 67
, this memory includes a clock generation circuit CKG generating an internal operation clock in response to control signals /RAS, /CAS and /WE, an address buffer ADB externally receiving an address signal AI, an X decoder XDEC and a Y decoder YDEC decoding the address signal in accordance with the clock generated by the clock generation circuit CKG, and a memory cell array MA transmitting/receiving data to/from an external device.
This memory further includes a self test circuit STC. The self test circuit STC includes a ROM storing a coded test procedure, a program counter PC, an address counter CA, a data generation circuit DG, a data compare circuit DC and a test clock generation circuit TCG.
In order to read a desired instruction from the ROM in a self test, the program counter PC specifies an address of the ROM storing the instruction. The ROM sequentially outputs the coded test procedure for controlling the program counter PC, the address counter AC, the data generation circuit DG, the data compare circuit DC and the test clock generation circuit TCG and progressing a memory test.
When such a self test circuit is built in the semiconductor memory device, a high-performance test can be executed with a simple tester, to reduce the test cost.
When interleaving a plurality of data in a data input/output circuit following the recent increase of the operating speed of the semiconductor device, however, the data may collide with each other when picked up by an externally connected circuit, or erroneous data may be picked up.
In a gigantic synchronous semiconductor memory device having a memory capacity reaching 1 Gbit, a skew of an internal signal, particularly a clock controlling the overall operation of the chip increases to limit the operating frequency of the chip. Particularly when receiving an externally inputted reference clock in a clock buffer and thereafter receiving an address, data and a command on the basis of the clock, the received clock must be distributed to input terminals for the address, the data and the command and a delay required for transmitting the clock limits the performance of the chip. Also when controlling an output buffer on the basis of the clock, the output is delayed by the clock skew to degrade the margin of output data received by an external device.
Following the increase of the operating speed of the semiconductor memory device, further, the following problem arises in an operation test during a step of fabricating the semiconductor memory device or in advance of shipment of products:
The time required for the test increases following increase of the memory capacity of the semiconductor memory device, to result in increase of the cost for the test as well as the fabrication cost for the products.
In order to prevent such increase the test time following increase of the memory capacity of the semiconductor memory device, a plurality of semiconductor memory devices are generally tested in parallel for improving the test efficiency. However, the aforementioned increase of the memory capacity of the semiconductor memory device results in increase of the bit number of an address signal supplied to the semiconductor memory device, a multi-bit structure of a data input/output interface and the like, and the number of semiconductor memory devices simultaneously testable in parallel is limited due to increase of the number of input pins and input/output pins for control signals in each semiconductor memory device.
In general, the number of chips of semiconductor memory devices simultaneously measurable in a tester depends on the number of pins provided on the tester and that of pins required by the chips, and is generally expressed as follows:
(number of pins provided in tester)/(number of pins required by chips)>(number of simultaneously measurable chips)
Assuming that the operating speed of a tester for testing a semiconductor memory device is improved following improvement of the operating speed of the semiconductor memory device itself, further, an extremely high-priced tester is required, to also result in increase of the test cost.
In addition, while a synchronous semiconductor memory device employs complicated systems such as BIST (built-in self test), generation of a clock by DLL (delay locked loop) and the like to reduce the cost and improve the function, it is difficult to externally observe operating states of these circuits.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a synchronous semiconductor memory device capable of reducing a test cost by reducing the number of terminals employed in testing thereby increasing the number of chips simultaneously measurable with a single tester and reducing the data rate for output data to be observed thereby allowing efficient testing without employing a high-priced tester of high performance.
Another object of the present invention is to provide a synchronous semiconductor memory device simplifying testing or evaluation of an internal circuit by rendering the state of the internal circuit, whose operation is not directly observable from outside, externally observable through an input/output circuit.
Briefly stated, the present invention is directed to a synchronous semiconductor memory device comprising a memory array, a read circuit, first and second data buses, a first output circuit and a first output node.
The read circuit batch-reads first and second stored data from the memory array in response to an address signal. The first and second data buses receive the first and second stored data respectively. The first output circuit receives the first and second stored data from the first and second data buses, performs different conversions in an normal operation and in a test, holds the converted data and thereafter outputs the same. The first output node receives the output of the first output circuit.
According to another aspect of the present invention, a synchronous semiconductor memory device comprises a memory array, a first match detection circuit, a shift register and a second match detection circuit.
The first match detection circuit receives a plurality of stored data batch-read from the memory array in response to a clock signal and detects a match. The shift register receives an output of the match detection circuit. The shift register includes serially connected first to n-th hold circuits (n: natural number of at least 2) fetching the stored data and outputting held data in response to the clock signal. The second match detection circuit determines whether or not all outputs of the first to n-th hold circuits match with each other.
According to still another aspect of the present invention, a synchronous semiconductor memory device comprises a memory array, a BIST (built-in self test) control circuit and a first terminal.
The BIST control circuit controls execution of a self test for the memory array, supplies an address signal and a command signal to the memory array, and transmits/receives stored d

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