Method of manufacturing an aluminum interconnect structure...

Details Method of manufacturing an aluminum interconnect structure... Method of manufacturing an aluminum interconnect structure...

1999-12-20

2002-05-07

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S626000, C438S627000, C438S629000, C438S631000, C438S633000, C438S643000, C438S645000, C438S648000, C438S653000, C438S656000, C438S672000, C438S685000, C438S687000, C438S688000

Reexamination Certificate

active

06383914

ABSTRACT:

BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to an interconnect structure of a semiconductor device and a method for manufacturing the same, specifically, a multiple-layered interconnect structure having aluminum as a main component which can suppress occurrence and growth of electro-migration (EM) and a method of manufacturing the same.
(b) Description of the Related Art
With the advance of high integration of semiconductor devices, the multi-layered interconnect structure in which a plurality of interconnect layers are connected to one another is more and more complicated.
An example of a method for manufacturing a conventional multi-layered interconnect structure will be described referring to
FIGS. 1A
to
1
F.
A bottom interconnect layer
14
is deposited on an undercoat dielectric film
12
overlying a silicon substrate (not shown), and an interlayer dielectric film
16
made of a plasma oxide is formed and flattened on the bottom interconnect layer
14
as shown in FIG.
1
A.
The bottom interconnect layer
14
includes, for example, an Al-Cu alloy film
14
a
constituting a main a interconnect body, a Ti layer
14
b
formed thereon and having a thickness of 25 nm, and a first TiN layer
14
c
having a thickness of 50 nm formed as a reflection preventing film in a photolithographic process. The Ti layer is formed for preventing formation of AlN during deposition of a first TiN layer
As shown in
FIG. 1B
, a through-hole
18
is formed in the interlayer dielectric film
16
to reach to the bottom interconnect layer
14
by a lithographic and etching process.
Then, as shown in
FIG. 1C
, a second TiN layer
20
20
is formed as a barrier metal layer on the entire surface of the wafer including the walls of the connection aperture
18
followed by formation of a tungsten (W) layer
22
on the second TiN layer
20
.
Then, as shown in
FIG. 1D
, the tungsten layer
22
is etched-back by employing a plasma etching method until the second TiN layer
20
is exposed, thereby forming a plug
24
of tungsten.
Then, as shown in
FIG. 1E
, a third TiN layer
26
having a thickness of 40 nm is deposited as a barrier metal layer on the second TiN layer
20
, followed by deposition of an Al—Cu alloy layer
28
on the third TiN layer
26
by sputtering at a temperature of 340° C. After the Al—Cu alloy layer
28
is cooled for 50 seconds, a Ti layer
30
having a thickness of 25 nm and a TiN layer
32
having a thickness of 50 nm are sequentially deposited on the Al—Cu alloy layer
28
by sputtering to form a top interconnect layer
34
.
The TiN layer
26
prevents excessive increase of a contact resistance between the Al—Cu alloy layer
28
and the tungsten layer
22
even if a void is formed in the Al—Cu alloy layer
28
on the plug
24
due to the EM.
Patterning of the TiN layer
32
, the Ti Layer
30
, the Al—Cu alloy layer
28
, the third TiN layer
26
and the second TiN layer
20
by a lithographic and dry-etching treating provides top interconnects
34
having a desired interconnect pattern as shown in FIG.
1
F.
In the above conventional interconnect structure, with the miniaturization thereof, the lifetime of the interconnect is considerably reduced due to the EM of the Al—Cu alloy layer to increase the interconnect resistance during the operation, and finally an interconnect deficiency such as a break down may be generated.
Since current is likely to be concentrated to the interconnect right above the plug, migration of the aluminum due to the EM may easily occur to make a void.
SUMMARY OF THE INVENTION
In view of the foregoing, an object of the present invention is to provide an interconnect structure which can suppress occurrence and growth of the EM of the aluminum and a method for manufacturing the same.
The present invention provides, in a first aspect thereof, an interconnect structure of a semiconductor device including: a silicon substrate; a bottom interconnect layer formed in a dielectric layer overlying the silicon substrate; a top interconnect layer having aluminum as a main component and connected with the bottom interconnect layer by way of a via plug formed in the dielectric layer; and a <111> oriented first barrier metal layer disposed between the via plug and the top interconnect layer.
The present invention provides, in a second aspect thereof, a method for manufacturing an interconnect structure of a semiconductor device, including the steps of: forming a bottom interconnect layer underlying a dielectric layer and overlying a silicon substrate; forming a through-hole in the dielectric layer to expose the bottom interconnect layer; depositing a first barrier metal layer overlying the dielectric layer and on an inner wall of the through-hole; depositing a metal layer on the first barrier metal layer for filling the through-hole; etching the metal layer and the first barrier metal layer until the dielectric film is exposed to thereby form a via plug of the metal layer and the barrier metal layer; depositing a second barrier metal layer on the dielectric film and the via plug; and depositing an interconnect layer of which a main component is aluminum on the second barrier metal layer.
In accordance with the interconnect structure of the present invention and fabrication from the method of the present invention, the increased <111> orientation of the aluminum of the top interconnects suppresses the occurrence and the growth of the EM of the aluminum. Accordingly, substantially no interconnect deficiencies due to the EM are generated to provide a reliable interconnect structure.
The above and other objects, features and advantages of the present invention will be more apparent from the following description.


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