Semiconductor memory device allowing effective detection of...

Details Semiconductor memory device allowing effective detection of... Semiconductor memory device allowing effective detection of...

2001-01-04

2002-01-22

Mai, Son (Department: 2818)

Static information storage and retrieval

Read/write circuit

Signals

C365S194000, C365S233100

Reexamination Certificate

active

06341089

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly a semiconductor memory device which allows a detection test of minute bit line leak failure, and therefore has improved reliability.
2. Description of the Background Art
In a semiconductor memory device, a row is activated in a memory cell array in accordance with a command and an address which are externally applied, and data is read from the memory cell at a selected column in the activated row.
FIG. 14
shows a circuit issuing row selection timing of a semiconductor memory device in the prior art.
Referring to
FIG. 14
, the row selection timing generating circuit in the conventional semiconductor memory device includes an active command generating circuit
132
and a precharge command generating circuit
134
which latch control signals int./RAS, int./CAS, int./WE and int./CS in synchronization with clock signal int.CLKI, and generate an active command ACT and a precharge command PRE, respectively, NAND circuits
136
and
138
which are cross-coupled, and receive a signal /ACT sent from active command generating circuit
132
and a signal /PRE sent from precharge command generating circuit
134
, respectively, a delay circuit
142
which delays a signal RAS sent from NAND circuit
136
, and issues a sense amplifier activating signal SS, an inverter
146
which inverts sense amplifier activating signal SS to issue a sense amplifier activating signal /SS, a BLEQ generating circuit
148
which issues an equalize signal BLEQ in accordance with sense amplifier activating signal SS and signal RAS, and a WLT generating circuit
150
which issues a signal WLT indicating timing for activating a word line in accordance with signal RAS.
FIG. 15
is an operation waveform diagram for showing a row selecting operation of the semiconductor memory device in the prior art.
Referring to
FIGS. 14 and 15
, command ACT which is determined in accordance with a combination of control signals int./RAS, int./CAS, int./WE and int./CS is input at a time t
1
so that active command generating circuit
132
activates signal /ACT to attain L-level. Thereby, a latch circuit formed of NAND circuits
136
and
138
latches signal /ACT to raise signal RAS from L-level to H-level.
Equalize signal BLEQ which equalizes and precharges a bit line pair is triggered by signal RAS to lower to L-level so that the bit line pair is released from the precharged state, and enters a floating state.
At a subsequent time t
2
, signal WLT rises to H-level, and the row decoder performing selection of the memory cell row selects one word line WLn, and sets the potential thereon to H-level. When word line WLn is activated to attain H-level, data written in the memory cell is transmitted onto the bit line pair so that a minute potential difference occurs between the paired bit lines.
At a time t
4
, the delay time of delay circuit
142
elapses. Thereby, sense amplifier activating signals SS and /SS are activated, and the sense amplifier operates to amplify the minute potential difference occurring on the bit line pair.
After the data is read, the bit lines are precharged again at a time t
5
, and the precharge command is applied for allowing a next read or write cycle.
Due to foreign substance such as dust, which was mixed in the manufacturing step, a minute leak may occur from the bit lines. In this case, the minute potential difference amplified by the sense amplifier is small. However, if an operation margin is present in the sense amplifier circuit, normal reading may be performed even when a leak from the bit line occurs to a certain extent. Even if a normal operation was performed in wafer state during an initial test, a leak may increase, e.g., in a burn-in test which is performed thereafter for removing initial failures, and therefore an operation failure may occur.
SUMMARY OF THE INVENTION
An object of the invention is to provide a semiconductor memory device, in which reliability is improved by allowing detection of a minute leak in an initial test before an acceleration test, and a manufacturing yield after the acceleration test such as a burn-in test can be improved.
In summary, the invention provides a semiconductor memory device for receiving a command in synchronization with a clock signal includes a memory array, a plurality of equalize circuits, a plurality of sense amplifiers and a control circuit.
The memory array includes a plurality of memory cells arranged in a matrix form having a plurality of rows and a plurality of columns, a plurality of word lines corresponding to the plurality of rows, respectively, and a plurality of bit line pairs corresponding to the plurality of columns, respectively. The plurality of equalize circuits apply predetermined potentials to the plurality of bit line pairs, respectively. The plurality of sense amplifiers amplify potential differences occurring on the plurality of bit line pairs, respectively. The control circuit controls reading of data from the memory array.
The control circuit includes a command recognizing portion for recognizing the command in accordance with a combination of a plurality of externally applied control signals, and issuing a timing reference signal providing a reference of timing of deactivation of the plurality of equalize circuits, activation of one of the plurality of word lines selected in accordance with an address signal, and activation of the plurality of sense amplifiers, a delay circuit for receiving and delaying the timing reference signal, and a signal delay control circuit for delaying the output of the delay circuit until activation of a first internal signal, and transmitting the delayed output to the plurality of sense amplifiers.
Accordingly, the invention can achieve the following major advantage. The signal forming the reference of the row activation is delayed during the test to a larger extent than that in the normal operation, and then is transmitted to the sense amplifier. Therefore, it is possible to detect a minute leak, which occurs between the bit lines and can not be removed in the normal operation test of the synchronous semiconductor memory device. Accordingly, the minute leak can be detected in the initial test before an acceleration test, and a burn-in test can be performed after performing replacement with a redundant memory cell row.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.


REFERENCES:
patent: 5528552 (1996-06-01), Kamisaki
patent: 5673231 (1997-09-01), Furutani
patent: 5848008 (1998-12-01), Kirihata et al.
patent: 5903512 (1999-05-01), Wong et al.
patent: 6046956 (2000-04-01), Yabe
patent: 6259640 (2001-07-01), Endo et al.
patent: 11-39899 (1999-02-01), None
patent: 11-149800 (1999-06-01), None
patent: 11-162195 (1999-06-01), None

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