Electrical computers and digital data processing systems: input/ – Input/output data processing
Reexamination Certificate
1999-10-29
2002-07-16
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
C710S011000, C710S033000, C710S061000, C709S201000, C709S232000
Reexamination Certificate
active
06421742
ABSTRACT:
BACKGROUND
1. Field of the Invention
This invention relates generally to methods and apparatus for transferring data over a network. In particular, the present invention relates to methods and apparatus for emulating an input/output unit when transferring data over a network.
2. Description of the Related Art
Conventional methods of transferring data between a host device, such as a server, and an input/output (I/O) unit, such as a block storage device, utilize a series of simple, basic level, commands sent from the central processing unit (CPU) of the host to the processor in a controller (usually implemented as a slot-based adaptor card) of the I/O unit via an I/O bus such as, for example, a Peripheral Component Interconnect (PCI) synchronous bus as described in the latest version of “PCI Local Bus Specification, Revision 2.1” set forth by the PCI Special Interest Group (SIG) on Jun. 1, 1995. In these methods, the host CPU has to direct each one of the steps taken by the controller of the I/O unit which results in delays in the data transfer and decreases in the performance of the host CPU.
For example, suppose that a host wishes to transfer data from a server to a hard disk via a network. The host CPU first stores the write command and its associated data within a block of host system memory. The host CPU transfers a command to the I/O controller via the I/O bus of the host and the network (a network interface controller (NIC) acts as the communications intermediary between the devices and the network and passes data blocks to and from the network in the speed and manner required by the network). This command tells the I/O controller that a new command has been issued. The I/O controller card must then read the data from system memory using a pointer, which is the value representing an address within the system memory where the data associated with the command can be found. (The pointer may be virtual or physical and the location of the data is not necessarily contiguous with the location of the command. Indeed, the data may be split, requiring a Scatter/Gather List (SGL) to describe the locations of the data.) To get the block of data from the system memory back to the I/O controller may require several separate fetches. The data is then subsequently written from the I/O controller to the hard disk itself. The host CPU must always load the data and the I/O controller must always separately read the write command to know where the data is located and perform the fetches to obtain the data. A similar load/store procedure occurs when a host CPU reads a block of data from the hard disk, i.e., a series of messages passed back and forth so the I/O controller can store the data in a block within the system memory.
The repetition of this conventional load/store procedure (illustrated generally in
FIG. 8
) of sending a command with pointer (step 1), waiting for and receiving a request for data (step 2) and subsequently sending the data in response to the request (step 3) has substantial inherent latencies and delays. Even though the host CPU performs optimally, the performance of the host can still be less than optimum because the procedure is very inefficient. The data transfers slow down the entire system and many CPU cycles will pass before they are completed. Although, the PCI bus architecture provides the most common accepted method used to extend computer systems for add-on arrangements (e.g., expansion cards) with new disk memory storage capabilities, it has performance limitations and scales poorly in server architectures.
A network may have a significant number of I/O devices which are of radically different types, store different kinds of data and/or vary from each other in the addressing sequence by which the data blocks containing the data are written and read out. Although not shown in
FIG. 1
, transport and other protocols (e.g., TCP, IP) are implemented at various levels of firmware and software in an I/O device to control, distinguish or review the transferred data in order to render the transfer of data over the network more reliable. The multiplexing and demultiplexing processes are computationally expensive and a host CPU must control the movement of the transfer data blocks into and out of the memory controller or I/O controller during the transfer of each data block.
SUMMARY
The present invention is directed to emulation in an I/O unit when transferring data over a network. In an example embodiment, a method of transferring data to or from an input/output unit across a network emulates a message passing protocol. A message sent from a host device to the input/output unit specifies the requested data transfer and is formatted in accordance with the message passing protocol. An emulation service software layer on the input/output unit translates the message into a corresponding series of data transfer operation instructions. The series of data transfer operation instructions have a different format than the format of the message passing protocol. The data transfer specified by the message is carried out by the operating system and hardware of a target device in the input/output unit using the series of data transfer operation instructions. After the data transfer is completed, a reply message is created in the emulation service software layer and the reply message is sent to the host device in a format according to the message passing protocol.
REFERENCES:
patent: 4858114 (1989-08-01), Heath et al.
patent: 5701516 (1997-12-01), Cheng et al.
patent: 5778189 (1998-07-01), Kimura et al.
patent: 5859981 (1999-01-01), Levin et al.
patent: 6035327 (2000-03-01), Buckley et al.
patent: 6128679 (2000-10-01), Beale et al.
patent: 6321279 (2001-11-01), Bonola
Antonelli Terry Stout & Kraus LLP
Gaffin Jeffrey
Intel Corporation
Mai Rijue
LandOfFree
Method and apparatus for emulating an input/output unit when... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for emulating an input/output unit when..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for emulating an input/output unit when... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2819242