Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-02-10
2002-04-23
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06378115
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of layout design for LSIs wherein a plurality of blocks is embedded in a chip, and further relates to a LSI (large Scale Integrated Circuit) manufacturing method, whereby top level signal wiring for connecting block pins of blocks can be arranged efficiently in a region among blocks, and a recording medium for storing such a LSI layout program.
2. Description of the Related Art
For ASIC (Application Specific Integrated Circuit) design carried out in a conventional manner, there are two types of layout design methods for circuit elements on a chip and the signal wiring connecting those: flat layout design methods and hierarchical layout design methods.
The flat layout design method is for arranging individual gates at the chip level and creating the wiring among the gates. The design period is tending to become longer for the large scale microchips of recent years and this is a disadvantage for a layout design method. Meanwhile, in hierarchical layout design methods, a chip is divided into a plurality of blocks; blocks which are already designed, or blocks designed and provided by a third party, are used for the blocks. The layout process then mainly involves the arrangement of those blocks and making the wiring among those blocks. Consequently, the design period is shorter than when using flat layout design methods. Also, when design changes become necessary, the layout is changed only for the corresponding block; this can further shorten the design period. Consequently, hierarchical layout design methods are more often used in the design of large scale integrated circuit devices, such as system LSIs.
Such hierarchical layout design methods are divided into bottom up hierarchical layout design methods and top down hierarchical layout design methods. In bottom up hierarchical layout design methods, the blocks are designed first and after the block designs are all completed, floor planning, including the arrangement of the plurality of blocks, is carried out. After which, the top level power main wiring in the region among the blocks, power lead wiring, and signal wiring to connect the block pins of the blocks are designed. As discussed above, the design of each block may be completed in advance in a vendor who designs LSIs, or completed in advance by a third party. Consequently, the positions of the block pins, which are the external terminals of the blocks, are already fixed at the stage where the plurality of blocks is arranged.
FIG. 1
shows problems with bottom up hierarchical layout design methods. Changes cannot be made to the frame (external frame) form, internal wiring layout, and block pin positions in blocks which are already designed. These blocks are called hard blocks.
FIG. 1
shows an example wherein hard blocks A and B are adjacent and the block pins
10
and
12
thereof are connected by top level (wiring level between blocks in the region outside the blocks) signal wiring
14
, located in the region between the blocks. As this figure clearly shows, the positions of the block pins of each hard block are not optimal and the top level signal wiring
14
for connecting those requires a wasteful wiring channel. Also, the length of the top level signal wiring
14
is not minimized; this leads to signal delays.
Top down hierarchical layout design methods were proposed as methods for correcting the defects of this bottom up hierarchical layout design method. These procedures use soft blocks for which block size, block frame form (aspect ratio), internal wiring, and block pin position are undetermined, and for which net list data, the information on connecting circuit elements, is determined.
Basically, the top down hierarchical layout design method initially determines soft block position, size, frame form, and block pins thereof, along with hard block position and establishes the top level power main wiring, in the region among the blocks. The length of the top level wiring is minimized. The method then arranges top level signal wiring and makes the layout within soft blocks. At the chip layout stage, the use of soft blocks allows for the optimization of soft block size, frame form, and block pins, depending on the combination of hard blocks and soft blocks used.
FIG. 2
shows a sample layout made using a top down hierarchical layout design method. Unlike
FIG. 1
, the block pins
16
of the soft block A are positioned at a location opposite to the block pins
12
of the hard block B. The length of the top level signal wiring
14
connecting those is therefore minimized and signal delays made small. Moreover, only the use of a vertical signal wiring layer becomes necessary and a wasteful wiring channel is not required.
FIG. 3
shows a problem with the top down hierarchical layout design methods. In the example in
FIG. 3
, two hard blocks A, C are adjacent to a soft block B. The block pins
16
of the soft block B are located at a position opposite to the block pins
10
of the adjacent hard block A. The top level signal wiring
14
, connecting those, is optimized as in FIG.
2
. However, the block pins
16
of the soft block B are not located at an optimal position with respect to the block pins
12
of the hard block C. As a result, the length of the top level signal wiring
18
, connecting the block pins
16
and
12
, is not minimized, signal delays occur, and a wasteful wiring channel becomes necessary.
In this way, conventional top down hierarchical layout design methods using soft blocks result in the heretofore unresolved problems in large scale integrated circuit devices, which use a greater number of blocks.
It is an object of the present invention to provide a layout method, which can optimize top level signal wiring for connections among blocks, and a recording medium for storing such a layout program.
It is another object of the present invention to provide a layout method, which can provide more flexibility in determining the arrangement of block pins of soft blocks and which can allow optimal positioning of block pins, and a recording medium for storing such a layout program.
It is another object of the present invention to provide a LSI manufacturing method, using a layout method with an increased degree of freedom in the number and arrangement of block pins of soft blocks, and a recording medium for storing a layout tool program for executing that layout method.
SUMMARY OF THE INVENTION
In order to achieve the aforementioned objects, the present invention resolves the problems of conventional top down hierarchical layout design methods by including the following in a top down hierarchical layout design method using soft block, in addition to determining the arrangement of block pin (called “soft pin”) in soft block: generating second block pin having the same potential as existing block pin; and moving block pin position to position opposite the block pin to be connected. The layout tool program of the present invention is therefore provided the functions of moving and generating soft pin, whereby the top level signal wiring in the region among the blocks is optimized, delay time is minimized, and the use of wasteful wiring channel is avoided for any combination of blocks.
In order to achieve the aforementioned objects, the present invention is a LSI (Large Scale Integrated Circuit) manufacturing method for embedding in a chip a plurality of blocks having prescribed functions and including a plurality of circuit elements and a plurality of block pins connecting externally,
wherein the plurality of blocks comprises hard blocks, wherein the block pin in the vicinity of the frame has fixed position at the layout design stage, and soft blocks, wherein the block pin in the vicinity of the frame has variable position at the layout design stage;
the manufacturing method comprising the steps of:
arranging the plurality of blocks on the chip;
moving first block pin in the soft block, to a position in the vicinity of the frame of the soft block, and opposite to fir
Smith Matthew
Speight Jibreel
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