Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-11-07
2002-07-02
Nguyen, Tuan H. (Department: 2813)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S392000, C257S393000, C327S408000, C327S325000
Reexamination Certificate
active
06414363
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device that has a low current consumption and performs high-speed operations using a low-voltage electrical source. More specifically, the present invention relates to a semiconductor device that is suitable for use in SRAM (static random access memory) and similar devices having a small standby current.
2. Description of the Related Art
In recent years, LSI (large-scale integrated circuits) and other such logic circuits have tended to operate using a low-voltage power source. The reason for this trend is that the withstanding voltage declines as the size of the transistors (abbreviated as “Tr” hereinafter) for forming logic circuits is reduced. Accordingly, the operating voltage must be reduced as a necessity. In addition, in order to install LSIs in portable information devices, it is essential for these LSI to be capable of being operated by the battery devices and therefore, these LSIs must be operated at low voltage region and in low power consumption.
However, there has also been a growing demand to increase the speed of operation of LSIs. Thus, it is not acceptable for the speed of operations to decrease in order to accomplish low voltage operation. In order to accomplish high-speed operation of a transistor while using a low voltage power source, a measure can be taken to reduce the amount of delay by lowering the transistor's threshold voltage (denoted as “Vt” hereinafter). Thus, as one example of conventional semiconductor devices, there is a design in which all of the circuits on a pass required to provide a high speed are formed of transistors having a low threshold voltage (referred to as “Conventional Example 1” hereinafter).
However, when the threshold voltage is reduced to enable high speed operation of the transistor, the transistor can no longer cut-off sufficiently. As a result, even in a no-bias state where the voltage between gate sources is “0”, a leak current, referred to as a “sub-threshold current”, will flow into the transistor. In the case of products typified by a low-power consuming SRAM in which there are many transistors and the standby current is very small, this sub-threshold current is too large to be ignored. However, if the threshold voltage of the transistor is raised in order to reduce the leak current, then a longer delay results, and an improvement in speed cannot be anticipated. Thus, in order to operate a semiconductor device at high speed with a low current consumption using a low voltage power source, it is necessary to satisfy the opposing requirements of reducing the transistor's threshold voltage and decreasing the leak current.
A design (referred to as “Conventional Example 2” hereinafter) such as shown in
FIG. 10
in which improvements have been added to Conventional Example 1 may be considered as a semiconductor device in which the effects from sub-threshold current have been eliminated. The semiconductor device of Conventional Example 2 is based on the technical concept disclosed in Japanese Patent Application, First Publication No. Hei 6-208790, and realizes four stages of inverters in a dependent connection. In this semiconductor device, only the threshold voltage of transistors that are ON in the standby state, in which logic circuits are not operated, has been reduced. Note that the example shown in the figure assumes that the electric potential of input node A in the standby state is at “L” level.
More specifically, with respect to the transistors forming the first inverter stage which is connected to input node A, the p-type (p-channel) transistor (MOSFET: metal oxide field effect transistor) Q
101
is a low Vt transistor having a low threshold voltage, while the n-type (n-channel) TrQ
102
is a high Vt transistor having a high threshold voltage. Note that the term “high Vt” as employed here device that the threshold voltage is higher than that of TrQ
101
, and does not specifically mean a transistor in which the threshold voltage has been increased. Accordingly, if sub-threshold currents can be blocked, then TrQ
102
can be formed using normal Vt transistors which do not change their threshold voltages. Since the distinction between n-type and p-type transistors is clear from the figures, they will not be discussed separately in the explanation that follows.
TrQ
103
~TrQ
108
are identical to TrQ
101
and TrQ
102
. TrQ
103
and TrQ
107
are the high Vt transistors and TrQ
104
and TrQ
108
are the low Vt transistors positioned at the second and final stages of inverters. The levels of the electric potentials at nodes A, A
1
, A
2
and A
3
in the standby state in
FIG. 10
are “L”, “H”, “L”, and “H”, respectively. In other words, the transistors that cut-off in the standby state are TrQ
102
, TrQ
103
, TrQ
106
and TrQ
107
. However, since these are all high Vt transistors, the subthreshold current is small. Accordingly, leak currents while in the standby state do not pose a problem as was the case in Conventional Example 1.
However, Conventional Example 2 has the following problems. Namely, high-speed operation is possible when the semiconductor device is in the active state for operating the internal logic circuits, since TrQ
101
, TrQ
104
, TrQ
105
, and TrQ
108
are low Vt transistors as in Conventional Example 1. Accordingly, low Vt TrQ
101
is ON when the input signal to input node A is falling, and the electric potential of node A
1
changes at high speed as a result. Conversely, high Vt TrQ
102
is ON when the input signal to node A is rising. In this case, the electric potential of node A
1
changes at low speed as compared to the case where the signal is falling, since the gate capacitance of a high Vt transistor is greater than that of a low Vt transistor.
Accordingly, the aforementioned Japanese Unexamined Patent Application, First Publication No. Hei 6-208790 broadens the channel width of the high Vt transistors so that the electric potential of node A
1
changes at high speed when there is a rising signal input to input node A. However, it is necessary to increase the size of the transistor in order to increase the channel width. Thus, there is an increase in chip size in a semiconductor device having a design such as conventional example 2.
A semiconductor device (“conventional example 3” hereinafter) such as shown in
FIG. 11
may be considered as a device of eliminating the effects of the sub-threshold current that was cited in the conventional example 1. As in the case of conventional example 2, the semiconductor device according to conventional example 3 is an example of the application of the technology disclosed in Japanese Patent Application, First Publication No. Hei 8-228145 to a design in which there are four stages of inverters. In
FIG. 11
, all of the transistors for the logic circuits on the pass from input node A to the output node B which must be high speed are formed of low Vt transistors. Namely, the conventional example 3 is identical to the conventional example 1 in this regard. In
FIG. 11
, low Vt TrQ
112
, TrQ
113
, TrQ
116
, and TrQ
117
are employed in place of the high Vt TrQ
102
, TrQ
103
, TrQ
106
and TrQ
107
that are shown in FIG.
10
.
In addition, high Vt TrQ
120
and TrQ
121
are provided in FIG.
11
. Of these, TrQ
120
is inserted in between the electric potential of the electric source and the source terminal for TrQ
101
, etc. The ON/OFF state of TrQ
120
is controlled by chip selecting signal /CS which is connected to the gate terminal. TrQ
121
is inserted in between the grounding electric potential and the source terminal for TrQ
112
, etc., and its ON/OFF state is controlled by a chip selecting signal CS that is connected to the gate terminal. Note that chip selecting signal CS is set at “H” level when the semiconductor device is in the active state shown in the figure, and is set at “L” level when the semiconductor device is in the standby state. The symbol “/” which precedes the signal name indicates an inverted signal. Thus, chip selecting signal /
Bhagawan V
Hayes & Soloway P.C.
NEC Corporation
Nguyen Tuan H.
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