Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1996-11-26
2002-09-03
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S286000
Reexamination Certificate
active
06445034
ABSTRACT:
The invention relates to an MOS transistor and more particularly to the achievement of desired channel dimensions.
One application of MOS transistors is in the fabrication of current mirror circuits which in its basic form comprise two transistors one of which is diode connected and has the input current applied to it and the other of which has its gate and source electrodes connected to the gate and source electrodes, respectively, of the first transistor and produces an output current at its drain electrode which is related to the input current. The relationship between the input and output currents depends on the channel width/length quotients of the transistors. In order to obtain an accurate ratio between the input and output currents it is normal to use a common channel length and vary only the channel width to obtain the desired current ratio because the relationship between the current and channel width is more linear than the relationship between current and channel length. Transistor dimensions, however, normally have to fit a resolution grid which means there is a minimum step between the possible channel widths available. Consequently there is a limit to the current ratios available, that is integer ratios may be obtained relatively easily but fractional ratios may be difficult to achieve with accuracy.
U.S. Pat. No. 5,362,988 discloses a mid rail generator circuit which uses a number of current mirror circuits. In this document all the channel lengths are kept the same and the channel widths are varied to produce the desired current ratios. In addition in order to obtain an integer multiplication a number of identical transistors are connected in parallel. While these arrangements are adequate to produce integer or simple fractional current ratios they become unwieldy for producing accurate non simple ratios unless transistor sizes are large.
The text book entitled “CMOS Analogue Circuit Design” by Philip E. Allen and Douglas R. Holberg, published by Holt, Rinehart and Winston Inc. (ISBN 0-03-006587-9) at pages 231 and 232 discusses the dimensioning of transistors in current amplifiers but is primarily concerned with integer multiplying factors. It states that it is usual to scale the channel widths rather than the channel length because the length tolerances are greater than the width tolerances due to out diffusion under the polysilicon gate.
It is an object of the invention to enable the construction of transistors having effective width to length ratios which can be defined in small increments without requiring large transistor sizes. It is a further object of the invention to enable the construction of current mirror circuits having non-integer current ratios using relatively small sized transistors.
The invention provides an MOS transistor in which the channel length and channel width are multiples of a minimum isolation grid unit characterised in that the channel length is greater for a portion of the width units than for the remainder of the width units.
By altering the length for some of the width units only a finer control of the transistor current for a given gate-source potential can be achieved and consequently a greater choice of current ratios in current mirror circuits constructed from such transistors can be obtained. It has been discovered that since the length is normally only altered by a small percentage of the overall length the less linear variation of current with channel length is not significant.
REFERENCES:
patent: 5362988 (1994-11-01), Hellums
patent: 54-46556 (1981-04-01), None
patent: 62-5668 (1987-01-01), None
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patent: 1-243591 (1989-09-01), None
patent: 2-156672 (1990-06-01), None
Runyan et al., Semiconductor Integrated Circuit Processing Technology, pp. 40-41 and 162, 1990.*
“CMOS Analog Circuit Design”, by P.E. Allen et al, pp. 231-232.
Hughes John B.
Moulding Kenneth W.
Crane Sara
Koninklijke Philips Electronics , N.V.
Waxler Aaron
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