Refresh-free semiconductor memory device

Details Refresh-free semiconductor memory device Refresh-free semiconductor memory device

2001-03-05

2002-04-23

Phan, Trong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

Reexamination Certificate

active

06377499

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly, relates to a semiconductor memory device capable of being stably accessed at a high speed with low current consumption. More particularly, the present invention relates to a memory cell structure of a semiconductor memory device such as DRAM (Dynamic Random Access Memory) that requires refresh of the data stored therein.
2. Description of the Background Art
FIG. 44
is a diagram schematically showing the structure of an Pay portion of a conventional DRAM (dynamic Random Access Memory).
FIG. 44
exemplarily shows 2-bit memory cells MC
1
and MC
2
, In
FIG. 44
, the memory cell MC
1
is located corresponding to the intersection of a word line WL
1
and a bit line BL, and the memory cell MC
2
is located corresponding to the intersection of a word line WL
2
and a bit line /BL. The memory cell MC
1
includes a memory cell capacitor CS
1
for storing information, and an access transistor MQ
1
for connecting the capacitor CS
1
to the bit line BL according to a word line selection signal &phgr;WL
1
on the word line WL
1
. The memory cell MC
2
includes a capacitor CS
2
for storing information, and an access transistor MQ
2
for connecting the capacitor CS
2
to the bit line /BL according to a word line selection signal &phgr;WL
2
on the word line WL
2
. These access transistors MQ
1
and MQ
2
are each formed of an N-channel MOS transistor (insulated-gate field effect transistor).
A sense amplifier SA activated in response to activation of a sense amplifier activation signal &phgr;SA for differentially amplifying and latching voltages on the bit lines BL and /BL is provided on the bit lines BL and /BL.
A cell plate voltage at a predetermined voltage level is applied to respective electrode nodes (cell plate nodes) of the capacitors CS
1
and CS
2
. In the memory cells MC
1
and MC
2
, charges corresponding to the stored data are retained at storage nodes SN
1
and SN
2
. Now, the operation of the DRAM shown in
FIG. 44
will be described with reference to a signal waveform diagram shown in FIG.
45
.
In the standby state, the word line selection signals &phgr;WL
1
and &phgr;WL
2
are both held at L level, and in the memory cells MC
1
and MC
2
, the access transistors MQ
1
and MQ
2
are both in the OFF state. The bit lines BL and /BL are precharged and equalized to an intermediate voltage level by a not-shown bit line precharge/equalize circuit.
When an active cycle is started, a row selection operation is performed according to an external address signal, and a word line corresponding to the addressed row is driven to the selected state. It is now assumed that the word line WL
1
is selected and the voltage level of the word line selection signal &phgr;WL
1
is raised, as shown in FIG.
45
. In this case, in the memory cell MC
1
, the access transistor MQ
1
is turned ON, and charges accumulated in the storage node SN
1
of the capacitor CS
1
are transmitted onto the bit line BL Since there is no memory cell at the intersection of the bit line /BL and word line WL
1
, the bit line /BL is kept at the precharge voltage level
FIG. 45
shows exemplary signal waveforms in the case where the L-level data is read from the memory cell MC
1
onto the bit line BL.
When the voltage difference between the bit lines BL and /BL is sufficiently developed, the sense amplifier activation signal &phgr;SA is activated. Accordingly, the sense amplifier SA differentially amplifies the voltages on the bit lines BL and /BL, so that the voltage levels on the bit lines BL and /BL are respectively driven to the ground voltage level and power supply voltage level and latched.
When the active cycle is completed, the word line selection signal &phgr;WL
1
is driven to the non-selected state, whereby the access transistor MQ
1
is turned OFF Subsequently, the sense amplifier activation signal &phgr;SA is deactivated, whereby the sense amplifier SA is rendered inactive. The bit lines BL and /BL are restored to the precharge voltage level.
As shown in
FIG. 44
, the memory cells MC
1
and MC
2
of the DRAM store information in the respective capacitors CS
1
and CS
2
in the form of charges. The storage node electrodes SN
1
and SN
2
of these capacitors are respectively connected to the access transistors MQ
1
and MQ
2
, and therefore the charges stored in the capacitors CS
1
and CS
2
are discharged to the substrate due to a leak current Moreover, in the case where the voltage levels on the bit lines BL and /BL change according to the selected memory cell data, the charges accumulated in the capacitor of the non-selected memory cell leak through the access transistor. Accordingly, in order to compensate for the change in the charge accumulation amount due to leakage of the charges stored in the storage nodes SN
1
and SN
2
, a refresh operation is performed in the DRAM. In the refresh operation of the memory cell MC
1
, the data in the memory cell MC
1
is read onto the bit line BL, and then amplified by the sense amplifier SA and rewritten to the memory cell MC
1
. Thus, the stored data in the memory cell MC
1
is restored. This refresh operation must be performed periodically.
In order to achieve increase in operation speed of the semiconductor memory device, reduction in current consumption and size of a processing system, and the like, the elements of the semiconductor memory device are reduced in dimensions. As a result of such dimensional reduction of the elements, the memory cell capacitors have a reduced area, and thus have a reduced capacitance value. The memory cell capacitor having a reduced capacitance value has a reduced charge storage amount (Q=V·C) even with the data at the same voltage level being written thereto. Therefore, even a slight amount of leak current causes a significant change in the voltage level of the storage data, thereby degrading the data retention characteristics. In order to compensate for such degradation in data retention characteristics, a refresh cycle must be reduced. However, an external processing device cannot access the DRAM during the refresh operation. Therefore, such a reduced refresh cycle results in degradation in performance of the processing system, Moreover, the reduced refresh cycle increases current consumption for the refresh operation. In particular, the condition of low standby current as required in the data retention mode (e.g., sleep mode) of a battery-driven portable equipment or the like cannot be sated. As a result, refreshing with such a reduced refresh cycle cannot be applied to applications such as the battery-driven portable equipment requiring low current consumption.
A pseudo SRAM (PSRAM) for operating the DRAM like an SRAM (Static Random Access Memory) is known as one method to solve the problems regarding the refresh of the DRAM This PSRAM is configured to successively perform, within a single memory access cycle, the two cycles of a normal data write/read cycle and a refresh cycle. Thus, the refresh can be performed in a single access cycle and can be concealed from the external access, thereby enabling the DRAM to be apparently operated as SRAM.
However, the PSRAM is requited to perform the operation of two cycles within a single access cycle, and therefore the cycle time cannot be reduced. In particular, it is difficult for the PSRAM to realize the operation cycle of 70 to 80 nanoseconds (ns) required for the SRAM in the current 0.18-micron manufacturing technology.
The structure in which a refresh port and a normal access port are separately provided so as to internally perform the refresh operation of the DRAM independently of the external access by using the refresh port is shown in, e.g., Japanese Patent Laid-Open Applications Nos. 2-21488, 61-11993 and 55-153194.
However, in these conventional examples, in the case where the memory tells are reduced in data retention characteristics due to the dimensional reduction thereof, the internal refresh interval must be reduced Therefore

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