Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2000-01-18
2002-07-02
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S270000
Reexamination Certificate
active
06414527
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a replica circuit for monitoring the critical path delay of a semiconductor circuit and a method for the same.
2. Description of the Related Art
Recent semiconductor circuits generally are reduced in power consumption by the method of lowering the power source voltage VDD.
Lowering the power source voltage is the most efficient way for reducing the power consumption of a semiconductor circuit (LSI) since the AC component of the power consumption of the LSI is proportional to the square of the power source voltage.
From this viewpoint, the method has recently been reported of dynamically controlling the power source voltage to meet with the operating frequency of the LSI and handle process variations.
In a control circuit using such a method, a replica circuit having the same power source voltage-delay characteristic as a critical path of the LSI is designed and the power source voltage is controlled so that the delay of the replica circuit does not exceed one cycle of the operating frequency.
Then, as shown in
FIG. 1
, several delay elements
2
are added as an extra margin to the replica circuit
1
over the critical path of the chip so as to give a larger delay than that of the critical path and thereby ensure the operation.
However, in the above device of the related art, since a fixed delay margin is built in, it becomes necessary to set a larger margin in order to handle deviations of actual devices from the design stage and ensure the necessary margin. Also, there is a possibility that the margin will be smaller than expected and that malfunctions will consequently occur.
When configuring the replica circuit and margin delay portion to match with the delay value by just transistor gates, in the same way as in an RC delay based on the wiring resistence R and wiring capacity C included in the actual device, since the delay characteristics are different from those of the transistor shown in
FIG. 2
, it is possible that the critical path of the chip can no longer be tracked due to changes in the delay due to voltage or temperature.
When building in delay elements as in the related art, adjustment is not possible after the chip is made, so if a problem turns up in the delay value, it is necessary to fix it by a design change.
Also, the RC delay and memory delay are generally customized. Therefore, the usual automatic placement and routing and other design techniques cannot be used for unit design of replica systems and therefore there was the problem of a poorer efficiency.
Therefore, there has been a demand for a circuit configuration of a more reliable replica system enabling flexible, efficient design.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device enabling configuration of a more reliable replica circuit flexibly and more efficiently and a method for the same.
To attain the above object, according to a first aspect of the present invention, there is provided a semiconductor device having a semiconductor circuit having a transfer path, a replica circuit for monitoring a delay time of a critical path of the semiconductor circuit, and a delay device adjustable in delay value arranged at least at one of an input side and output side of the replica circuit.
Preferably, the adjustable delay device includes delay elements having different delay characteristics. The different delay characteristics of the delay elements may be a transistor gate delay characteristic, wiring resistence and wiring capacity delay characteristic, and memory delay characteristic.
Preferably, the semiconductor device further comprises a register and a means for adjusting a delay value of the adjustable delay device based on data set in the register.
Alternatively, the semiconductor device further comprises an input terminal of an external signal and a means for adjusting a delay value of the adjustable delay device based on an external signal input to the input terminal.
Preferably, the delay elements having different delay characteristics are used as standard cells and at least one of the adjustable delay device and replica circuit is configured by arrangements of the standard cells of the delay elements.
According to a second aspect of the present invention, there is provided a semiconductor device comprising a semiconductor circuit having a transfer path, a replica circuit configured by a circuit having an equivalent power source voltage-delay characteristic to that of a transfer path used as a critical path of the semiconductor circuit and propagating a reference signal to monitor the critical path of the semiconductor device, an adjustable delay device arranged at least at one of an input side and output side of the replica circuit and capable of being adjusting in its delay value, and a voltage control circuit for generating a power source voltage of a value based on monitoring results of the replica circuit and supplying the same to the semiconductor circuit and the replica circuit.
Preferably, the adjustable delay device comprises delay elements having different delay characteristics. The different delay characteristics of the delay elements may be a transistor gate delay characteristic, wiring resistence and wiring capacity delay characteristic, and memory delay characteristic.
Preferably, the semiconductor device further comprises a register and a means for adjusting a delay value of the adjustable delay device based on data set in the register.
Alternatively, the semiconductor device further comprises an input terminal of an external signal and a means for adjusting a delay value of the adjustable delay device based on an external signal input to the input terminal.
Preferably, the delay components having different the delay elements having different delay characteristics are used as standard cells and at least one of the adjustable delay device and replica circuit is configured by arrangements of the standard cells of the delay elements.
According to a third aspect of the present invention, there is provided a semiconductor device comprising a semiconductor circuit having a transfer path and a replica circuit for monitoring a delay time of a critical path of the semiconductor circuit, the replica circuit comprising a delay device capable of being adjusted in its delay time.
Preferably, the adjustable delay device comprises delay elements having different delay characteristics. The different delay characteristics of the delay elements may be a transistor gate delay characteristic, wiring resistence and wiring capacity delay characteristic, and memory delay characteristic.
Preferably, the semiconductor device further comprises a register and a means for adjusting a delay value of the adjustable delay device based on data set in the register.
Alternatively, the semiconductor device further comprises a register and a means for adjusting a delay value of the adjustable delay device based on data set in the register.
According to a fourth aspect of the present invention, there is provided a semiconductor device comprising a semiconductor circuit having a transfer path and a replica circuit for propagating a reference signal to monitor a delay time of a critical path of the semiconductor circuit, the replica circuit comprising a plurality of replica portions including delay devices, a connection selecting means for connecting the plurality of replica portions in parallel or in series with respect to an input of the reference signal upon receiving a selection signal, and a selecting means for selecting as a monitor signal an output signal of the largest delay amount from outputs of the plurality of replica portions.
Preferably, the delay devices comprise delay elements having different delay characteristics and are capable of being adjusted in delay values by settings. The different delay characteristics of the delay elements may be a transistor gate delay characteristic, wiring resistence and wiring capacity delay characteristic, an
Kondo Tetsuo
Seki Takahiro
Seno Katsunori
Cunningham Terry D.
Kananen, Esq. Ronald P.
Rader & Fishman & Grauer, PLLC
Sony Corporation
Tra Quan
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