Method and apparatus for generating layout pattern

Details Method and apparatus for generating layout pattern Method and apparatus for generating layout pattern

2008-03-04

2008-03-04

Lin, Sun James (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07340708

ABSTRACT:
A method includes: obtaining process technology definition data related to a process technology of each layer forming a basic cell, from a process technology definition file defining process technology definition data related to a process technology for use in fabricating a semiconductor integrated circuit, thereby holding a process technology definition table; obtaining device structure data including data related to a device template which defines a structure of each layer of the basic cell and data related to the structure of the layer defined in accordance with the device template, from a device structure definition file, thereby holding the obtained device structure data as a device structure definition table; and determining the structure of each layer defined in accordance with the device template held as the obtained device structure data, thereby generating the layout pattern of the basic cell forming the semiconductor integrated circuit.

REFERENCES:
patent: 2005/0278673 (2005-12-01), Kawachi
patent: 2006/0045325 (2006-03-01), Zavadsky et al.
patent: 08-096002 (1996-04-01), None
patent: 2000-195958 (2000-07-01), None
patent: 2003-036280 (2003-02-01), None

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