Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2008-07-08
2008-07-08
Pham, Thanh V (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S581000, C438S583000, C438S630000, C438S649000, C438S651000, C438S721000, C438S658000, C438S664000, C438S682000, C438S755000, C257SE21190, C257SE21165, C257SE21438
Reexamination Certificate
active
07396764
ABSTRACT:
The technology which can improve the performance of a MOS transistor in which all the regions of the gate electrode were silicided is offered.A gate insulating film and a gate electrode of an nMOS transistor are laminated and formed in this order on a semiconductor substrate. A source/drain region of the nMOS transistor is formed in the upper surface of the semiconductor substrate. The source/drain region is silicided after siliciding all the regions of the gate electrode. Thus, silicide does not cohere in the source/drain region by the heat treatment at the silicidation of the gate electrode by siliciding the source/drain region after the silicidation of the gate electrode. Therefore, the electric resistance of the source/drain region is reduced and junction leak can be reduced. As a result, the performance of the nMOS transistor improves.
REFERENCES:
patent: 1-183851 (1989-07-01), None
patent: 7-245396 (1995-09-01), None
patent: 8-46057 (1996-02-01), None
patent: 11-121745 (1999-04-01), None
patent: 2000-252462 (2000-09-01), None
patent: 2002-319670 (2002-10-01), None
U.S. Appl. No. 11/319,740, filed Dec. 29, 2005, Kuroi.
U.S. Appl. No. 11/381,654, filed May 4, 2006, Komori.
B. Tavel, et al., “Totally Silicided (CoSi2) Polysilicon: a novel approach to very low-resistive gate (˜2 Ω/□) without metal CMP nor etching”, International Electron Device Meeting, 2001, pp. 1-4.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Pham Thanh V
Renesas Technology Corp.
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