Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-05-06
2008-05-06
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07370304
ABSTRACT:
An LSI designing system includes a memory;, a database configured to store a layout layer definition file, and a control section configured to refer to the database to build up a plurality of layout layers in the memory based on the layout layer definition file. The plurality of layout layers are provided for extending directions of patterns in one of physical layers of an LSI to be formed. The control section divides each of the patterns into pattern structures based on the extending directions, and assigns each of the pattern structures to a corresponding one of the plurality of layout layers.
REFERENCES:
patent: 6033812 (2000-03-01), Miyagawa
patent: 6308143 (2001-10-01), Segawa
patent: 6813756 (2004-11-01), Igarashi et al.
patent: 2002/0184606 (2002-12-01), Ohba et al.
patent: 1135602 (2004-01-01), None
Chiang Jack
Foley & Lardner LLP
NEC Electronics Corporation
Tat Binh
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